View PIC16C54-XTIS_6751497.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2000 microchip technology inc. preliminary ds30453c-page 1 pic16c5x devices included in this data sheet: ?pic16c54 pic16cr54 pic16c55 pic16c56 pic16cr56 pic16c57 pic16cr57 pic16c58 pic16cr58 high-performance risc cpu: only 33 single word instructions to learn all instructions are single cycle (200 ns) except for program branches which are two-cycle operating speed: dc - 20 mhz clock input dc - 200 ns instruction cycle 12-bit wide instructions 8-bit wide data path seven or eight special function hardware registers two-level deep hardware stack direct, indirect and relative addressing modes for data and instructions note: 16c5x refers to all revisions of the part (i.e., 16c54 refers to 16c54, 16c54a, and 16c54c), unless specifically called out otherwise. device pins i/o eprom/ rom ram pic16c54 18 12 512 25 pic16c54a 18 12 512 25 pic16c54c 18 12 512 25 pic16cr54a 18 12 512 25 pic16cr54c 18 12 512 25 pic16c55 28 20 512 24 pic16c55a 28 20 512 24 pic16c56 18 12 1k 25 pic16c56a 18 12 1k 25 pic16cr56a 18 12 1k 25 pic16c57 28 20 2k 72 pic16c57c 28 20 2k 72 pic16cr57c 28 20 2k 72 pic16c58b 18 12 2k 73 pic16cr58b 18 12 2k 73 peripheral features: 8-bit real time clock/counter (tmr0) with 8-bit programmable prescaler power-on reset (por) device reset timer (drt) watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation programmable code protection power saving sleep mode selectable oscillator options: - rc: low-cost rc oscillator - xt: standard crystal/resonator - hs: high-speed crystal/resonator - lp: power saving, low-frequency crystal cmos technology: low-power, high-speed cmos eprom/rom technology fully static design wide-operating voltage and temperature range: - eprom commercial/industrial 2.0v to 6.25v - rom commercial/industrial 2.0v to 6.25v - eprom extended 2.5v to 6.0v - rom extended 2.5v to 6.0v low-power consumption - < 2 ma typical @ 5v, 4 mhz -15 a typical @ 3v, 32 khz - < 0.6 a typical standby current (with wdt disabled) @ 3v, 0 c to 70 c note: in this document, figure and table titles refer to all varieties of the part number indi- cated, (i.e., the title "figure 14-1: load conditions - pic16c54a", also refers to pic16lc54a and pic16lv54a parts) unless specifically called out otherwise. eprom/rom-based 8-bit cmos microcontroller series
pic16c5x ds30453c-page 2 preliminary ? 2000 microchip technology inc. pin diagrams pdip, soic, windowed cerdip pic16cr54 pic16c58 pic16cr58 pic16c54 ra1 ra0 osc1/clkin osc2/clkout v dd v dd rb7 rb6 rb5 rb4 ra2 ra3 t0cki mclr /v pp v ss v ss rb0 rb1 rb2 rb3 ? 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ssop pic16c56 pic16cr56 pic16cr54 pic16c58 pic16cr58 pic16c54 pic16c56 pic16cr56 ra2 ra3 t0cki mclr /v pp v ss rb0 rb1 rb2 rb3 ? 1 2 3 4 5 6 7 8 9 10 18 17 16 15 14 13 12 11 ra1 ra0 osc1/clkin osc2/clkout v dd rb7 rb6 rb5 rb4 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 pdip, soic, windowed cerdip pic16c57 pic16c55 mclr /v pp osc1/clkin osc2/clkout rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 rb7 rb6 rb5 t0cki v dd v ss ra0 ra1 ra2 ra3 rb0 rb1 rb2 rb3 rb4 ? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ssop pic16c55 v dd v ss pic16cr57 pic16cr57 t0cki v dd n/c v ss n/c ra0 ra1 ra2 ra3 rb0 rb1 rb2 rb3 rb4 mclr /v pp osc1/clkin osc2/clkout rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 rb7 rb6 rb5 pic16c57
? 2000 microchip technology inc. preliminary ds30453c-page 3 pic16c5x device differences note 1: if you change from this device to another device, please verify oscillator characteristics in your application. device voltage range oscillator selection (program) oscillator process technology (microns) rom equivalent mclr filter pic16c54 2.5-6.25 factory see note 1 1.2 pic16cr54a no pic16c54a 2.0-6.25 user see note 1 0.9 ? no pic16c54c 2.5-5.5 user see note 1 0.7 pic16cr54c yes pic16c55 2.5-6.25 factory see note 1 1.7 ? no pic16c55a 2.5-5.5 user see note 1 0.7 ? yes pic16c56 2.5-6.25 factory see note 1 1.7 ? no pic16c56a 2.5-5.5 user see note 1 0.7 pic16cr56a yes pic16c57 2.5-6.25 factory see note 1 1.2 ? no pic16c57c 2.5-5.5 user see note 1 0.7 pic16cr57c yes pic16c58b 2.5-5.5 user see note 1 0.7 pic16cr58b yes pic16cr54a 2.5-6.25 factory see note 1 1.2 n/a yes pic16cr54c 2.5-5.5 factory see note 1 0.7 n/a yes pic16cr56a 2.5-5.5 factory see note 1 0.7 n/a yes pic16cr57c 2.5-5.5 factory see note 1 0.7 n/a yes pic16cr58b 2.5-5.5 factory see note 1 0.7 n/a yes note: the table shown above shows the generic names of the pic16c5x devices. for device varieties, please refer to section 2.0.
pic16c5x ds30453c-page 4 preliminary ? 2000 microchip technology inc. table of contents 1.0 general description......................................................................................................... ............................................................. 5 2.0 pic16c5x device varieties ................................................................................................... ...................................................... 7 3.0 architectural overview ...................................................................................................... ........................................................... 9 4.0 memory organization ......................................................................................................... ........................................................ 15 5.0 i/o ports ................................................................................................................... .................................................................. 25 6.0 timer0 module and tmr0 register ............................................................................................. .............................................. 27 7.0 special features of the cpu ................................................................................................. ..................................................... 31 8.0 instruction set summary ..................................................................................................... ....................................................... 43 9.0 development support......................................................................................................... ........................................................ 55 10.0 electrical characteristics - pic16c54/55/56/57 ............................................................................. ............................................ 61 11.0 dc and ac characteristics - pic16c54/55/56/57.............................................................................. ........................................ 73 12.0 electrical characteristics - pic16cr54a .................................................................................... ............................................... 81 13.0 electrical characteristics - pic16c54a..................................................................................... ................................................. 93 14.0 dc and ac characteristics - pic16c54a ...................................................................................... .......................................... 105 15.0 electrical characteristics - pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/c58b/cr58b......................................... 115 16.0 dc and ac characteristics - pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/c58b/cr58b ..................................... 127 17.0 packaging information...................................................................................................... ........................................................ 137 appendix a: compatibility ...................................................................................................... ............................................................ 149 index .......................................................................................................................... ........................................................................ 151 on-line support................................................................................................................ ................................................................. 153 reader response ................................................................................................................ .............................................................. 154 pic16c5x product identification system ........................................................................................ .................................................. 155 pic16c54/55/56/57 product identification system ............................................................................... ............................................ 156 to our valued customers most current data sheet to automatically obtain the most up-to-date version of this data sheet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number. e.g., ds30000a is version a of document ds30000. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. errata an errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the re vi- sion of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: microchip ? s worldwide web site; http://www.microchip.com your local microchip sales office (see last page) the microchip corporate literature center; u.s. fax: (480) 786-7277 when contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (inclu de liter- ature number) you are using. corrections to this data sheet we constantly strive to improve the quality of all our products and documentation. we have spent a great deal of time to ensure that this document is correct. however, we realize that we may have missed a few things. if you find any information that is mi ssing or appears in error, please: fill out and mail in the reader response form in the back of this data sheet. e-mail us at webmaster@microchip.com. we appreciate your assistance in making this a better document.
? 2000 microchip technology inc. preliminary ds30453c-page 5 pic16c5x 1.0 general description the pic16c5x from microchip technology is a family of low-cost, high performance, 8-bit, fully static, eprom/rom-based cmos microcontrollers. it employs a risc architecture with only 33 single word/single cycle instructions. all instructions are sin- gle cycle (200 ns) except for program branches which take two cycles. the pic16c5x delivers performance an order of magnitude higher than its competitors in the same price category. the 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. the easy to use and easy to remember instruction set reduces development time significantly. the pic16c5x products are equipped with special fea- tures that reduce system cost and power requirements. the power-on reset (por) and device reset timer (drt) eliminate the need for external reset circuitry. there are four oscillator configurations to choose from, including the power-saving lp (low power) oscillator and cost saving rc oscillator. power saving sleep mode, watchdog timer and code protection features improve system cost, power and reliability. the uv erasable cerdip packaged versions are ideal for code development, while the cost-effective one time programmable (otp) versions are suitable for production in any volume. the customer can take full advantage of microchip ? s price leadership in otp microcontrollers, while benefiting from the otp ? s flexibility. the pic16c5x products are supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low-cost development program- mer and a full featured programmer. all the tools are supported on ibm ? pc and compatible machines. 1.1 applications the pic16c5x series fits perfectly in applications rang- ing from high-speed automotive and appliance motor control to low-power remote transmitters/receivers, pointing devices and telecom processors. the eprom technology makes customizing application programs (transmitter codes, motor speeds, receiver frequen- cies, etc.) extremely fast and convenient. the small footprint packages, for through hole or surface mount- ing, make this microcontroller series perfect for applica- tions with space limitations. low-cost, low-power, high performance, ease of use and i/o flexibility make the pic16c5x series very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, replacement of ? glue ? logic in larger systems, co-processor applications).
pic16c5x ds30453c-page 6 preliminary ? 2000 microchip technology inc. table 1-1: pic16c5x family of devices pic16c54 pic16cr54 pic16c55 pic16c56 pic16cr56 clock maximum frequency of operation (mhz) 20 20 20 20 20 memory eprom program memory (x12 words) 512 ? 512 1k ? rom program memory (x12 words) ? 512 ?? 1k ram data memory (bytes) 25 25 24 25 25 peripherals timer module(s) tmr0 tmr0 tmr0 tmr0 tmr0 features i/o pins 12 12 20 12 12 number of instructions 33 33 33 33 33 packages 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 28-pin dip, soic; 28-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop all picmicro ? family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. pic16c57 pic16cr57 pic16c58 pic16cr58 clock maximum frequency of operation (mhz) 20 20 20 20 memory eprom program memory (x12 words) 2k ? 2k ? rom program memory (x12 words) ? 2k ? 2k ram data memory (bytes) 72 72 73 73 peripherals timer module(s) tmr0 tmr0 tmr0 tmr0 features i/o pins 20 20 12 12 number of instructions 33 33 33 33 packages 28-pin dip, soic; 28-pin ssop 28-pin dip, soic; 28-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop all picmicro ? family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability.
? 2000 microchip technology inc. preliminary ds30453c-page 7 pic16c5x 2.0 pic16c5x device varieties a variety of frequency ranges and packaging options are available. depending on application and production requirements, the proper device option can be selected using the information in this section. when placing orders, please use the pic16c5x product identifica- tion system at the back of this data sheet to specify the correct part number. for the pic16c5x family of devices, there are four device types, as indicated in the device number: 1. c , as in pic16 c 54c. these devices have eprom program memory and operate over the standard voltage range. 2. lc , as in pic16 lc 54a. these devices have eprom program memory and operate over an extended voltage range. 3. cr , as in pic16 cr 54a. these devices have rom program memory and operate over the standard voltage range. 4. lcr , as in pic16 lcr 54a. these devices have rom program memory and operate over an extended voltage range. 2.1 uv erasable devices (eprom) the uv erasable versions, offered in cerdip pack- ages, are optimal for prototype development and pilot programs. uv erasable devices can be programmed for any of the four oscillator configurations. microchip ? s picstart ? and pro mate ? programmers both support program- ming of the pic16c5x. third party programmers also are available. refer to the third party guide for a list of sources. 2.2 one-time-programmable (otp) devices the availability of otp devices is especially useful for customers expecting frequent code changes and updates. the otp devices, packaged in plastic packages, per- mit the user to program them once. in addition to the program memory, the configuration bits must be pro- grammed. 2.3 quick-turnaround-production (qtp) devices microchip offers a qtp programming service for fac- tory production orders. this service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabi- lized. the devices are identical to the otp devices but with all eprom locations and configuration bit options already programmed by the factory. certain code and prototype verification procedures apply before produc- tion shipments are available. please contact your microchip technology sales office for more details. 2.4 serialized quick-turnaround-production (sqtp ) devices microchip offers the unique programming service where a few user-defined locations in each device are programmed with different serial numbers. the serial numbers may be random, pseudo-random or sequen- tial. the devices are identical to the otp devices but with all eprom locations and configuration bit options already programmed by the factory. serial programming allows each device to have a unique number which can serve as an entry code, password or id number. 2.5 read only memory (rom) devices microchip offers masked rom versions of several of the highest volume parts, giving the customer a low cost option for high volume, mature products. sm
pic16c5x ds30453c-page 8 preliminary ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. preliminary ds30453c-page 9 pic16c5x 3.0 architectural overview the high performance of the pic16c5x family can be attributed to a number of architectural features com- monly found in risc microprocessors. to begin with, the pic16c5x uses a harvard architecture in which program and data are accessed on separate buses. this improves bandwidth over traditional von neumann architecture where program and data are fetched on the same bus. separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. instruction opcodes are 12-bits wide making it possible to have all single word instructions. a 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. a two-stage pipeline overlaps fetch and execution of instructions. consequently, all instructions (33) execute in a single cycle (200ns @ 20mhz) except for program branches. the pic16c54/cr54 and pic16c55 address 512 x 12 of program memory, the pic16c56/cr56 address 1k x 12 of program memory, and the pic16c57/cr57 and pic16c58/cr58 address 2k x 12 of program memory. all program memory is internal. the pic16c5x can directly or indirectly address its register files and data memory. all special function reg- isters including the program counter are mapped in the data memory. the pic16c5x has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. this symmetrical nature and lack of ? special optimal situations ? make programming with the pic16c5x simple yet efficient. in addition, the learning curve is reduced significantly. the pic16c5x device contains an 8-bit alu and work- ing register. the alu is a general purpose arithmetic unit. it performs arithmetic and boolean functions between data in the working register and any register file. the alu is 8-bits wide and capable of addition, sub- traction, shift and logical operations. unless otherwise mentioned, arithmetic operations are two's comple- ment in nature. in two-operand instructions, typically one operand is the w (working) register. the other operand is either a file register or an immediate con- stant. in single operand instructions, the operand is either the w register or a file register. the w register is an 8-bit working register used for alu operations. it is not an addressable register. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc), and zero (z) bits in the status register. the c and dc bits operate as a borrow and digit borrow out bit, respec- tively, in subtraction. see the subwf and addwf instructions for examples. a simplified block diagram is shown in figure 3-1, with the corresponding device pins described in table 3-1.
pic16c5x ds30453c-page 10 preliminary ? 2000 microchip technology inc. figure 3-1: pic16c5x series block diagram wdt time out 8 stack 1 stack 2 eprom/rom 512 x 12 to 2048 x 12 instruction register instruction decoder watchdog timer configuration word oscillator/ timing & control general purpose register file (sram) 24, 25, 72 or 73 bytes wdt/tmr0 prescaler option reg. ? option ? ? sleep ? ? code protect ? ? osc select ? direct address tmr0 from w from w ? tris 5 ? ? tris 6 ? ? tris 7 ? fsr trisa porta trisb portc trisc portb from w t0cki pin 9-11 9-11 12 12 8 w 4 4 4 data bus 8 8 8 8 8 8 8 alu status from w clkout 8 9 6 5 5-7 osc1 osc2 mclr literals pc ? disable ? 2 ra<3:0> rb<7:0> rc<7:0> (28-pin devices only) direct ram address
? 2000 microchip technology inc. preliminary ds30453c-page 11 pic16c5x table 3-1: pinout description - pic16c54s, pic16cr54, pic16c56, pic16cr56, pic16c58, pic16cr58 name dip, soic no. ssop no. i/o/p type input levels description ra0 ra1 ra2 ra3 17 18 1 2 19 20 1 2 i/o i/o i/o i/o ttl ttl ttl ttl bi-directional i/o port rb0 rb1 rb2 rb3 rb4 rb5 rb6 rb7 6 7 8 9 10 11 12 13 7 8 9 10 11 12 13 14 i/o i/o i/o i/o i/o i/o i/o i/o ttl ttl ttl ttl ttl ttl ttl ttl bi-directional i/o port t0cki 3 3 i st clock input to timer0. must be tied to v ss or v dd, if not in use, to reduce current consumption. mclr /v pp 4 4 i st master clear (reset) input/programming voltage input. this pin is an active low reset to the device. voltage on the mclr /v pp pin must not exceed v dd to avoid unintended entering of programming mode. osc1/clkin 16 18 i st oscillator crystal input/external clock source input. osc2/clkout 15 17 o ? oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. v dd 14 15,16 p ? positive supply for logic and i/o pins. v ss 55,6p ? ground reference for logic and i/o pins. legend: i = input, o = output, i/o = input/output, p = power, ? = not used, ttl = ttl input, st = schmitt trigger input
pic16c5x ds30453c-page 12 preliminary ? 2000 microchip technology inc. table 3-2: pinout description - pic16c55, pic16c57, pic16cr57 name dip, soic no. ssop no. i/o/p type input levels description ra0 ra1 ra2 ra3 6 7 8 9 5 6 7 8 i/o i/o i/o i/o ttl ttl ttl ttl bi-directional i/o port rb0 rb1 rb2 rb3 rb4 rb5 rb6 rb7 10 11 12 13 14 15 16 17 9 10 11 12 13 15 16 17 i/o i/o i/o i/o i/o i/o i/o i/o ttl ttl ttl ttl ttl ttl ttl ttl bi-directional i/o port rc0 rc1 rc2 rc3 rc4 rc5 rc6 rc7 18 19 20 21 22 23 24 25 18 19 20 21 22 23 24 25 i/o i/o i/o i/o i/o i/o i/o i/o ttl ttl ttl ttl ttl ttl ttl ttl bi-directional i/o port t0cki 1 2 i st clock input to timer0. must be tied to v ss or v dd if not in use to reduce current consumption. mclr 28 28 i st master clear (reset) input. this pin is an active low reset to the device. osc1/clkin 27 27 i st oscillator crystal input/external clock source input. osc2/clkout 26 26 o ? oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. v dd 23,4p ? positive supply for logic and i/o pins. v ss 41,14p ? ground reference for logic and i/o pins. n/c 3,5 ?? ? unused, do not connect. legend: i = input, o = output, i/o = input/output, p = power, ? = not used, ttl = ttl input, st = schmitt trigger input
? 2000 microchip technology inc. preliminary ds30453c-page 13 pic16c5x 3.1 clocking scheme/instruction cycle the clock input (osc1/clkin pin) is internally divided by four to generate four non-overlapping quadrature clocks, namely q1, q2, q3 and q4. internally, the pro- gram counter is incremented every q1 and the instruc- tion is fetched from program memory and latched into the instruction register in q4. it is decoded and exe- cuted during the following q1 through q4. the clocks and instruction execution flow are shown in figure 3-2 and example 3-1. 3.2 instruction flow/pipelining an instruction cycle consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipe- lined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effec- tively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ), then two cycles are required to complete the instruction (example 3-1). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the instruction register in cycle q1. this instruc- tion is then decoded and executed during the q2, q3 and q4 cycles. data memory is read during q2 (oper- and read) and written during q4 (destination write). figure 3-2: clock/instruction cycle example 3-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clkout (rc mode) pc pc+1 pc+2 fetch inst (pc) execute inst (pc-1) fetch inst (pc+1) execute inst (pc) fetch inst (pc+2) execute inst (pc+1) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is ? flushed ? from the pipeline, while the new instruction is being fetched and then executed. 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf porta, bit3 fetch 4 flush fetch sub_1 execute sub_1
pic16c5x ds30453c-page 14 preliminary ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. preliminary ds30453c-page 15 pic16c5x 4.0 memory organization pic16c5x memory is organized into program memory and data memory. for devices with more than 512 bytes of program memory, a paging scheme is used. program memory pages are accessed using one or two status register bits. for devices with a data memory register file of more than 32 registers, a banking scheme is used. data memory banks are accessed using the file selection register (fsr). 4.1 program memory organization the pic16c54, pic16cr54 and pic16c55 have a 9-bit program counter (pc) capable of addressing a 512 x 12 program memory space (figure 4-1). the pic16c56 and pic16cr56 have a 10-bit program counter (pc) capable of addressing a 1k x 12 program memory space (figure 4-2). the pic16cr57, pic16c58 and pic16cr58 have an 11-bit program counter capable of addressing a 2k x 12 program memory space (figure 4-3). accessing a location above the physically implemented address will cause a wraparound. a nop at the reset vector location will cause a restart at location 000h. the reset vector for the pic16c54, pic16cr54 and pic16c55 is at 1ffh. the reset vector for the pic16c56 and pic16cr56 is at 3ffh. the reset vector for the pic16c57, pic16cr57, pic16c58, and pic16cr58 is at 7ffh. figure 4-1: pic16c54/cr54/c55 program memory map and stack pc<8:0> stack level 1 stack level 2 user memory space call, retlw 9 000h 1ffh reset vector 0ffh 100h on-chip program memory figure 4-2: pic16c56/cr56 program memory map and stack figure 4-3: pic16c57/cr57/c58/ cr58 program memory map and stack pc<9:0> stack level 1 stack level 2 user memory space 10 000h 1ffh reset vector 0ffh 100h on-chip program memory (page 0) on-chip program memory (page 1) 200h 2ffh 300h 3ffh call, retlw pc<10:0> stack level 1 stack level 2 user memory space 11 000h 1ffh reset vector 0ffh 100h on-chip program memory (page 0) on-chip program memory (page 1) on-chip program memory (page 2) on-chip program memory (page 3) 200h 3ffh 2ffh 300h 400h 5ffh 4ffh 500h 600h 7ffh 6ffh 700h call, retlw
pic16c5x ds30453c-page 16 preliminary ? 2000 microchip technology inc. 4.2 data memory organization data memory is composed of registers, or bytes of ram. therefore, data memory for a device is specified by its register file. the register file is divided into two functional groups: special function registers and general purpose registers. the special function registers include the tmr0 reg- ister, the program counter (pc), the status register, the i/o registers (ports) and the file select register (fsr). in addition, special purpose registers are used to control the i/o port configuration and prescaler options. the general purpose registers are used for data and control information under command of the instructions. for the pic16c54, pic16cr54, pic16c56 and pic16cr56, the register file is composed of 7 special function registers and 25 general purpose registers (figure 4-4). for the pic16c55, the register file is composed of 8 special function registers and 24 general purpose registers. for the pic16c57 and pic16cr57, the register file is composed of 8 special function registers, 24 general purpose registers and up to 48 additional general purpose registers that may be addressed using a banking scheme (figure 4-5). for the pic16c58 and pic16cr58, the register file is composed of 7 special function registers, 25 general purpose registers and up to 48 additional general purpose registers that may be addressed using a banking scheme (figure 4-6). 4.2.1 general purpose register file the register file is accessed either directly or indirectly through the file select register (fsr). the fsr reg- ister is described in section 4.7. figure 4-4: pic16c54, pic16cr54, pic16c55, pic16c56, pic16cr56 register file map file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr porta portb general purpose registers note 1: not a physical register. see section 4.7. 2: pic16c55 only, in all other devices this is implemented as a a general purpose register. 0fh 10h portc (2) 08h
pic16c5x ds30453c-page 17 preliminary ? 2000 microchip technology inc. figure 4-5: pic16c57/cr57 register file map figure 4-6: pic16c58/cr58 register file map file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr porta portb 0fh 10h bank 0 bank 1 bank 2 bank 3 3fh 30h 20h 2fh 5fh 50h 40h 4fh 7fh 70h 60h 6fh general purpose registers general purpose registers general purpose registers general purpose registers general purpose registers portc 08h addresses map back to addresses in bank 0. note 1: not a physical register. see section 4.7. fsr<6:5> 00 01 10 11 file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr porta portb 0fh 10h bank 0 bank 1 bank 2 bank 3 3fh 30h 20h 2fh 5fh 50h 40h 4fh 7fh 70h 60h 6fh general purpose registers general purpose registers general purpose registers general purpose registers general purpose registers addresses map back to addresses in bank 0. note 1: not a physical register. see section 4.7. fsr<6:5> 00 01 10 11
pic16c5x ds30453c-page 18 preliminary ? 2000 microchip technology inc. 4.2.2 special function registers the special function registers are registers used by the cpu and peripheral functions to control the opera- tion of the device (table 4-1). the special registers can be classified into two sets. the special function registers associated with the ? core ? functions are described in this section. those related to the operation of the peripheral features are described in the section for each peripheral feature. table 4-1: special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on mclr and wdt reset n/a tris i/o control registers (trisa, trisb, trisc) 1111 1111 1111 1111 n/a option contains control bits to configure timer0 and timer0/wdt prescaler --11 1111 --11 1111 00h indf uses contents of fsr to address data memory (not a physical register) xxxx xxxx uuuu uuuu 01h tmr0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu 02h (1) pcl low order 8 bits of pc 1111 1111 1111 1111 03h status pa2 pa1 pa0 to pd zdcc 0001 1xxx 000q quuu 04h fsr indirect data memory address pointer 1xxx xxxx (3) 1uuu uuuu (3) 05h porta ? ? ? ? ra3 ra2 ra1 ra0 ---- xxxx ---- uuuu 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 07h (2) portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu legend: shaded boxes = unimplemented or unused, ? = unimplemented, read as ? 0 ? (if applicable) x = unknown, u = unchanged, q = see the tables in section 7.7 for possible values. note 1: the upper byte of the program counter is not directly accessible. see section 4.5 for an explanation of how to access these bits. 2: file address 07h is a general purpose register on the pic16c54, pic16cr54, pic16c56, pic16cr56, pic16c58 and pic16cr58. 3: for the pic16c54 and pic16c55, the value on reset is 111x xxxx and for mclr and wdt reset, the value is 111u uuuu .
pic16c5x ds30453c-page 19 preliminary ? 2000 microchip technology inc. 4.3 status register this register contains the arithmetic status of the alu, the reset status, and the page preselect bits for pro- gram memories larger than 512 words. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf , bsf and movwf instructions be used to alter the status regis- ter because these instructions do not affect the z, dc or c bits from the status register. for other instruc- tions which do affect status bits, see section 8.0, instruction set summary. register 4-1: status register (address:03h) r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x pa2 pa1 pa0 to pd z dc c r = readable bit w = writable bit - n = value at por reset bit7 6 5 4 3 2 1 bit0 bit 7: pa2 : this bit unused at this time. use of the pa2 bit as a general purpose read/write bit is not recommended, since this may affect upward compatibility with future products. bit 6-5: pa<1:0> : program page preselect bits (pic16c56/cr56)(pic16c57/cr57)(pic16c58/cr58) 00 = page 0 (000h - 1ffh) - pic16c56/cr56, pic16c57/cr57, pic16c58/cr58 01 = page 1 (200h - 3ffh) - pic16c56/cr56, pic16c57/cr57, pic16c58/cr58 10 = page 2 (400h - 5ffh) - pic16c57/cr57, pic16c58/cr58 11 = page 3 (600h - 7ffh) - pic16c57/cr57, pic16c58/cr58 each page is 512 words. using the pa<1:0> bits as general purpose read/write bits in devices which do not use them for program page preselect is not recommended since this may affect upward compatibility with future products. bit 4: to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3: pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2: z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1: dc : digit carry/borrow bit (for addwf and subwf instructions) addwf 1 = a carry from the 4th low order bit of the result occurred 0 = a carry from the 4th low order bit of the result did not occur subwf 1 = a borrow from the 4th low order bit of the result did not occur 0 = a borrow from the 4th low order bit of the result occurred bit 0: c : carry/borrow bit (for addwf , subwf and rrf , rlf instructions) addwf subwf rrf or rlf 1 = a carry occurred 1 = a borrow did not occur loaded with lsb or msb, respectively 0 = a carry did not occur 0 = a borrow occurred
pic16c5x ds30453c-page 20 preliminary ? 2000 microchip technology inc. 4.4 option register the option register is a 6-bit wide, write-only regis- ter which contains various control bits to configure the timer0/wdt prescaler and timer0. by executing the option instruction, the contents of the w register will be transferred to the option reg- ister. a reset sets the option<5:0> bits. register 4-2: option register u-0 u-0 w-1 w-1 w-1 w-1 w-1 w-1 ? ? t0cs t0se psa ps2 ps1 ps0 w = writable bit u = unimplemented bit - n = value at por reset bit7 6 5 4 3 2 1 bit0 bit 7-6: unimplemented . bit 5: t0cs : timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clkout) bit 4: t0se : timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler assigned to the wdt 0 = prescaler assigned to timer0 bit 2-0: ps<2:0> : prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value timer0 rate wdt rate
? 2000 microchip technology inc. preliminary ds30453c-page 21 pic16c5x 4.5 program counter as a program instruction is executed, the program counter (pc) will contain the address of the next pro- gram instruction to be executed. the pc value is increased by one, every instruction cycle, unless an instruction changes the pc. for a goto instruction, bits 8:0 of the pc are provided by the goto instruction word. the pc latch (pcl) is mapped to pc<7:0> (figure 4-7 and figure 4-8). for the pic16c56, pic16cr56, pic16c57, pic16cr57, pic16c58 and pic16cr58, a page num- ber must be supplied as well. bit5 and bit6 of the sta- tus register provide page information to bit9 and bit10 of the pc (figure 4-8 and figure 4-9). for a call instruction, or any instruction where the pcl is the destination, bits 7:0 of the pc again are pro- vided by the instruction word. however, pc<8> does not come from the instruction word, but is always cleared (figure 4-7 and figure 4-8). instructions where the pcl is the destination, or modify pcl instructions, include movwf pc, addwf pc, and bsf pc,5. for the pic16c56, pic16cr56, pic16c57, pic16cr57, pic16c58 and pic16cr58, a page num- ber again must be supplied. bit5 and bit6 of the sta- tus register provide page information to bit9 and bit10 of the pc (figure 4-8 and figure 4-9). note: because pc<8> is cleared in the call instruction, or any modify pcl instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any pro- gram memory page (512 words long). figure 4-7: loading of pc branch instructions - pic16c54, pic16cr54, pic16c55 figure 4-8: loading of pc branch instructions - pic16c56/pic16cr56 pc 87 0 pcl pc 87 0 pcl reset to ? 0 ? instruction word instruction word goto instruction call or modify pcl instruction pa<1:0> 2 status pc 87 0 pcl 9 10 pa<1:0> 2 status pc 87 0 pcl 9 10 instruction word reset to ? 0 ? instruction word 70 70 goto instruction call or modify pcl instruction
pic16c5x ds30453c-page 22 preliminary ? 2000 microchip technology inc. figure 4-9: loading of pc branch instructions - pic16c57/pic16cr57, and pic16c58/pic16cr58 4.5.1 paging considerations ? pic16c56/cr56, pic16c57/cr57 and pic16c58/cr58 if the program counter is pointing to the last address of a selected memory page, when it increments it will cause the program to continue in the next higher page. however, the page preselect bits in the status reg- ister will not be updated. therefore, the next goto , call or modify pcl instruction will send the program to the page specified by the page preselect bits (pa0 or pa<1:0>). for example, a nop at location 1ffh (page 0) incre- ments the pc to 200h (page 1). a goto xxx at 200h will return the program to address 0xxh on page 0 (assuming that pa<1:0> are clear). to prevent this, the page preselect bits must be updated under program control. 4.5.2 effects of reset the program counter is set upon a reset, which means that the pc addresses the last location in the last page (e.g., the reset vector). the status register page preselect bits are cleared upon a reset, which means that page 0 is pre-selected. therefore, upon a reset, a goto instruction at the reset vector location will automatically cause the pro- gram to jump to page 0. pa<1:0> 2 status pc 87 0 pcl 9 10 pa<1:0> 2 status pc 87 0 pcl 9 10 instruction word reset to ? 0 ? instruction word 70 70 goto instruction call or modify pcl instruction 4.6 stack pic16c5x devices have a 10-bit or 11-bit wide, two-level hardware push/pop stack. a call instruction will push the current value of stack 1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. if more than two sequential call ? s are executed, only the most recent two return addresses are stored. a retlw instruction will pop the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. if more than two sequential retlw ? s are executed, the stack will be filled with the address previously stored in level 2. note that the w register will be loaded with the literal value specified in the instruction. this is particularly useful for the implementation of data look-up tables within the pro- gram memory. for the retlw instruction, the pc is loaded with the top of stack (tos) contents. all of the devices covered in this data sheet have a two-level stack. the stack has the same bit width as the device pc. 4.7 indirect data addressing; indf and fsr registers the indf register is not a physical register. addressing indf actually addresses the register whose address is contained in the fsr register (fsr is a pointer ). this is indirect addressing. example 4-1: indirect addressing register file 08 contains the value 10h register file 09 contains the value 0ah load the value 08 into the fsr register a read of the indf register will return the value of 10h increment the value of the fsr register by one (fsr = 09h) a read of the indr register now will return the value of 0ah. reading indf itself indirectly (fsr = 0) will produce 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). a simple program to clear ram locations 10h-1fh using indirect addressing is shown in example 4-2. example 4-2: how to clear ram using indirect addressing movlw 0x10 ;in itialize pointer movwf fsr ; to ram next clrf indf ;cl ear indf register incf fsr,f ;inc pointer btfsc fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue
? 2000 microchip technology inc. preliminary ds30453c-page 23 pic16c5x the fsr is either a 5-bit (pic16c54, pic16cr54, pic16c55), 6-bit (pic16c56, pic16cr56), or 7-bit (pic16c57s, pic16cr57, pic16c58, pic16cr58) wide register. it is used in conjunction with the indf register to indirectly address the data memory area. the fsr<4:0> bits are used to select data memory addresses 00h to 1fh. pic16c54, pic16cr54, pic16c55: these do not use banking. fsr<6:5> bits are unimplemented and read as ? 1 ? s. pic16c57, pic16cr57, pic16c58, pic16cr58: fsr<6:5> are the bank select bits and are used to select the bank to be addressed ( 00 = bank 0, 01 =bank 1, 10 = bank 2, 11 = bank 3). figure 4-10: direct/indirect addressing note 1: for register map detail see section 4.2. bank location select location select bank select indirect addressing direct addressing data memory (1) 0fh 10h bank 0 bank 1 bank 2 bank 3 0 4 5 6 (fsr) 10 00 01 11 00h 1fh 3fh 5fh 7fh (opcode) 0 4 5 6 (fsr) addresses map back to addresses in bank 0.
pic16c5x ds30453c-page 24 preliminary ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. preliminary ds30453c-page 25 pic16c5x 5.0 i/o ports as with any other register, the i/o registers can be written and read under program control. however, read instructions (e.g., movf portb,w ) always read the i/o pins independent of the pin ? s input/output modes. on reset, all i/o ports are defined as input (inputs are at hi-impedance) since the i/o control registers (trisa, trisb, trisc) are all set. 5.1 porta porta is a 4-bit i/o register. only the low order 4 bits are used (ra<3:0>). bits 7-4 are unimplemented and read as '0's. 5.2 portb portb is an 8-bit i/o register (portb<7:0>). 5.3 portc portc is an 8-bit i/o register for pic16c55, pic16c57 and pic16cr57. portc is a general purpose register for pic16c54, pic16cr54, pic16c56, pic16c58 and pic16cr58. 5.4 tris registers the output driver control registers are loaded with the contents of the w register by executing the tris f instruction. a '1' from a tris register bit puts the corresponding output driver in a hi-impedance (input) mode. a '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. the tris registers are ? write-only ? and are set (output drivers disabled) upon reset. note: a read of the ports reads the pins, not the output data latches. that is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low. 5.5 i/o interfacing the equivalent circuit for an i/o port pin is shown in figure 5-1. all ports may be used for both input and output operation. for input operations these ports are non-latching. any input must be present until read by an input instruction (e.g., movf portb, w ). the out- puts are latched and remain unchanged until the output latch is rewritten. to use a port pin as output, the corre- sponding direction control bit (in trisa, trisb) must be cleared (= 0). for use as an input, the corresponding tris bit must be set. any i/o pin can be programmed individually as input or output. figure 5-1: equivalent circuit for a single i/o pin note 1: i/o pins have protection diodes to v dd and v ss . data bus q d q ck q d q ck p n wr port tris ? f ? data tris rd port v ss v dd i/o pin (1) w reg latch latch reset table 5-1: summary of port registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on mclr and wdt reset n/a tris i/o control registers (trisa, trisb, trisc) 1111 1111 1111 1111 05h porta ? ? ? ? ra3 ra2 ra1 ra0 ---- xxxx ---- uuuu 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 07h portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu legend: shaded boxes = unimplemented, read as ? 0 ? , ? = unimplemented, read as '0', x = unknown, u = unchanged
pic16c5x ds30453c-page 26 preliminary ? 2000 microchip technology inc. 5.6 i/o programming considerations 5.6.1 bi-directional i/o ports some instructions operate internally as read followed by write operations. the bcf and bsf instructions, for example, read the entire port into the cpu, execute the bit operation and re-write the result. caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. for example, a bsf operation on bit5 of portb will cause all eight bits of portb to be read into the cpu, bit5 to be set and the portb value to be written to the output latches. if another bit of portb is used as a bi-direc- tional i/o pin (say bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the cpu and rewritten to the data latch of this particular pin, overwriting the previous content. as long as the pin stays in the input mode, no problem occurs. however, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. example 5-1 shows the effect of two sequential read-modify-write instructions (e.g., bcf, bsf , etc.) on an i/o port. a pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin ( ? wired-or ? , ? wired-and ? ). the resulting high output currents may damage the chip. example 5-1: read-modify-write instructions on an i/o port ;initial port settings ; portb<7:4> inputs ; portb<3:0> outputs ;portb<7:6> have external pull-ups and are ;not connected to other circuitry ; ; port latch port pins ; ---------- ---------- bcf portb, 7 ;01pp pppp 11pp pppp bcf portb, 6 ;10pp pppp 11pp pppp movlw 03fh ; tris portb ;10pp pppp 10pp pppp ; ;note that the user may have expected the pin ;values to be 00pp pppp. the 2nd bcf caused ;rb7 to be latched as the pin value (high). 5.6.2 successive operations on i/o ports the actual write to an i/o port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (figure 5-2). therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that file to be read into the cpu, is executed. otherwise, the previous state of that pin may be read into the cpu rather than the new state. when in doubt, it is better to separate these instructions with a nop or another instruction not accessing this i/o port. figure 5-2: successive i/o operation pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetched rb<7:0> movwf portb nop port pin sampled here nop movf portb,w instruction executed movwf portb (write to portb) nop movf portb,w this example shows a write to portb followed by a read from portb. (read portb) port pin written here
? 2000 microchip technology inc. preliminary ds30453c-page 27 pic16c5x 6.0 timer0 module and tmr0 register the timer0 module has the following features: 8-bit timer/counter register, tmr0 - readable and writable 8-bit software programmable prescaler internal or external clock select - edge select for external clock figure 6-1 is a simplified block diagram of the timer0 module, while figure 6-2 shows the electrical structure of the timer0 input. timer mode is selected by clearing the t0cs bit (option<5>). in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if tmr0 register is written, the increment is inhibited for the following two cycles (figure 6-3 and figure 6-4). the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting the t0cs bit (option<5>). in this mode, timer0 will increment either on every rising or falling edge of pin t0cki. the incrementing edge is determined by the source edge select bit t0se (option<4>). clearing the t0se bit selects the rising edge. restrictions on the external clock input are discussed in detail in section 6.1. the prescaler assignment is controlled in software by the control bit psa (option<3>). clearing the psa bit will assign the prescaler to timer0. the prescaler is not readable or writable. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. section 6.2 details the operation of the prescaler. a summary of registers associated with the timer0 module is found in table 6-1. note: the prescaler may be used by either the timer0 module or the watchdog timer, but not both. figure 6-1: timer0 block diagram figure 6-2: electrical structure of t0cki pin note 1: bits t0cs, t0se, psa, ps2, ps1 and ps0 are located in the option register. 2: the prescaler is shared with the watchdog timer (figure 6-6). t0cki t0se (1) 0 1 1 0 pin t0cs (1) f osc /4 programmable prescaler (2) sync with internal clocks tmr0 reg psout (2 cycle delay) psout data bus 8 psa (1) ps2, ps1, ps0 (1) 3 sync v ss v ss r in schmitt trigger n input buffer t0cki pin note 1: esd protection circuits. (1) (1)
pic16c5x ds30453c-page 28 preliminary ? 2000 microchip technology inc. figure 6-3: timer0 timing: internal clock/no prescale figure 6-4: timer0 timing: internal clock/prescale 1:2 table 6-1: registers associated with timer0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on mclr and wdt reset 01h tmr0 timer0 - 8-bit real-time clock/counter xxxx xxxx uuuu uuuu n/a option ? ? t0cs t0se psa ps2 ps1 ps0 --11 1111 --11 1111 legend: shaded cells: unimplemented bits, - = unimplemented, x = unknown, u = unchanged. pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch timer0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 t0+1 t0+2 nt0 nt0 nt0 nt0+1 nt0+2 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch timer0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 nt0+1 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 t0+1 nt0 instruction execute t0
? 2000 microchip technology inc. preliminary ds30453c-page 29 pic16c5x 6.1 using timer0 with an external clock when an external clock input is used for timer0, it must meet certain requirements. the external clock require- ment is due to internal phase clock (t osc ) synchroniza- tion. also, there is a delay in the actual incrementing of timer0 after synchronization. 6.1.1 external clock synchronization when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki with the internal phase clocks is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks (figure 6-5). therefore, it is necessary for t0cki to be high for at least 2t osc (and a small rc delay of 20 ns) and low for at least 2t osc (and a small rc delay of 20 ns). refer to the electrical specification of the desired device. when a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type pres- caler so that the prescaler output is symmetrical. for the external clock to meet the sampling requirement, the ripple counter must be taken into account. there- fore, it is necessary for t0cki to have a period of at least 4t osc (and a small rc delay of 40 ns) divided by the prescaler value. the only requirement on t0cki high and low time is that they do not violate the mini- mum pulse width requirement of 10 ns. refer to param- eters 40, 41 and 42 in the electrical specification of the desired device. 6.1.2 timer0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the timer0 mod- ule is actually incremented. figure 6-5 shows the delay from the external clock edge to the timer incrementing. figure 6-5: timer0 timing with external clock increment timer0 (q4) external clock input or q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 timer0 t0 t0 + 1 t0 + 2 small pulse misses sampling external clock/prescaler output after sampling (3) prescaler output (2) (1) note 1: delay from clock input change to timer0 increment is 3tosc to 7tosc. (duration of q = tosc). therefore, the error in measuring the interval between two edges on timer0 input = 4tosc max. 2: external clock if no prescaler selected, prescaler output otherwise. 3: the arrows indicate the points in time where sampling occurs.
pic16c5x ds30453c-page 30 preliminary ? 2000 microchip technology inc. 6.2 prescaler an 8-bit counter is available as a prescaler for the timer0 module, or as a postscaler for the watchdog timer (wdt), respectively (section 6.1.2). for simplic- ity, this counter is being referred to as ? prescaler ? throughout this data sheet. note that the prescaler may be used by either the timer0 module or the wdt, but not both. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the wdt, and vice-versa. the psa and ps<2:0> bits (option<3:0>) determine prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf 1, movwf 1, bsf 1,x, etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the wdt. the prescaler is nei- ther readable nor writable. on a reset, the prescaler contains all '0's. 6.2.1 switching prescaler assignment the prescaler assignment is fully under software control (i.e., it can be changed ? on the fly ? during program exe- cution). to avoid an unintended device reset, the fol- lowing instruction sequence (example 6-1) must be executed when changing the prescaler assignment from timer0 to the wdt. example 6-1: changing prescaler (timer0 wdt) 1.clrwdt ;clear wdt 2.clrf tmr0 ;clear tmr0 & prescaler 3.movlw '00xx1111 ? b ;these 3 lines (5, 6, 7) 4.option ; are required only if ; desired 5.clrwdt ;ps<2:0> are 000 or ;001 6.movlw '00xx1xxx ? b ;set postscaler to 7.option ; desired wdt rate to change prescaler from the wdt to the timer0 mod- ule, use the sequence shown in example 6-2. this sequence must be used even if the wdt is disabled. a clrwdt instruction should be executed before switching the prescaler. example 6-2: changing prescaler (wdt timer0) clrwdt ;clear wdt and ;prescaler movlw 'xxxx0xxx' ;select tmr0, new ;prescale value and ;clock source option figure 6-6: block diagram of the timer0/wdt prescaler t0cki t0se pin t cy ( = f osc /4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m mux watchdog timer psa 0 1 0 1 wdt time-out ps<2:0> 8 note: t0cs, t0se, psa, ps<2:0> are bits in the option register. psa wdt enable bit 0 1 0 1 data bus 8 psa t0cs m u x m u x u x
? 2000 microchip technology inc. preliminary ds30453c-page 31 pic16c5x 7.0 special features of the cpu what sets a microcontroller apart from other proces- sors are special circuits that deal with the needs of real-time applications. the pic16c5x family of micro- controllers has a host of such features intended to max- imize system reliability, minimize cost through elimination of external components, provide power sav- ing operating modes and offer code protection. these features are: oscillator selection reset power-on reset (por) device reset timer (drt) watchdog timer (wdt) sleep code protection id locations the pic16c5x family has a watchdog timer, which can be shut off only through configuration bit wdte. it runs off of its own rc oscillator for added reliability. there is an 18 ms delay provided by the device reset timer (drt), intended to keep the chip in reset until the crystal oscillator is stable. with this timer on-chip, most applications need no external reset circuitry. the sleep mode is designed to offer a very low cur- rent power-down mode. the user can wake-up from sleep through external reset or through a watch- dog timer time-out. several oscillator options are also made available to allow the part to fit the application. the rc oscillator option saves system cost while the lp crystal option saves power. a set of configuration bits are used to select various options. 7.1 configuration bits configuration bits can be programmed to select various device configurations. two bits are for the selection of the oscillator type and one bit is the watchdog timer enable bit. nine bits are code protection bits (figure 7-1 and figure 7-2) for the pic16c54, pic16cr54, pic16c56, pic16cr56, pic16c58, and pic16cr58 devices. qtp or rom devices have the oscillator configuration programmed at the factory and these parts are tested accordingly (see "product identification system" dia- grams in the back of this data sheet). figure 7-1: configuration word for pic16cr54a/c54c/cr54c/c55a/c56a/cr56a/c57c/ cr57c/c58b/cr58b cp cp cp cp cp cp cp cp cp wdte fosc1 fosc0 register: config address (1) : fffh bit1110987654321 bit0 bit 11-3: cp: code protection bits 1 = code protection off 0 = code protection on bit 2: wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: f osc 1:f osc 0: oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: refer to the pic16c5x programming specification (literature number ds30190) to determine how to access the configuration word.
pic16c5x ds30453c-page 32 preliminary ? 2000 microchip technology inc. figure 7-2: configuration word for pic16c54/c54a/c55/c56/c57 ? ? ? ? ? ? ? ? cp wdte fosc1 fosc0 register: config address (1) :fffh bit1110987654321 bit0 bit 11-4: unimplemented: read as ? 0 ? bit 3: cp: code protection bit. 1 = code protection off 0 = code protection on bit 2: wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: f osc 1:f osc 0: oscillator selection bits (2) 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: refer to the pic16c5x programming specifications (literature number ds30190) to determine how to access the configuration word. 2: pic16lv54a supports xt, rc and lp oscillator only. pic16lv58a supports xt, rc and lp oscillator only.
? 2000 microchip technology inc. preliminary ds30453c-page 33 pic16c5x 7.2 oscillator configurations 7.2.1 oscillator types pic16c5xs can be operated in four different oscillator modes. the user can program two configuration bits (f osc <1:0>) to select one of these four modes: lp: low power crystal xt: crystal/resonator hs: high speed crystal/resonator rc: resistor/capacitor 7.2.2 crystal oscillator / ceramic resonators in xt, lp or hs modes, a crystal or ceramic resonator is connected to the osc1/clkin and osc2/clkout pins to establish oscillation (figure 7-3). the pic16c5x oscillator design requires the use of a paral- lel cut crystal. use of a series cut crystal may give a fre- quency out of the crystal manufacturers specifications. when in xt, lp or hs modes, the device can have an external clock source drive the osc1/clkin pin (figure 7-4). figure 7-3: crystal operation (or ceramic resonator) (hs, xt or lp osc configuration) note: not all oscillator selections available for all parts. see section 7.1. note 1: see capacitor selection tables for recommended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf varies with the crystal chosen (approx. value = 10 m ? ). c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to internal logic rs (2) pic16c5x figure 7-4: external clock input operation (hs, xt or lp osc configuration) table 7-1: capacitor selection for ceramic resonators - pic16c5x, pic16cr5x table 7-2: capacitor selection for crystal oscillator - pic16c5x, pic16cr5x osc type resonator freq cap. range c1 cap. range c2 xt 455 khz 2.0 mhz 4.0 mhz 22-100 pf 15-68 pf 15-68 pf 22-100 pf 15-68 pf 15-68 pf hs 4.0 mhz 8.0 mhz 16.0 mhz 15-68 pf 10-68 pf 10-22 pf 15-68 pf 10-68 pf 10-22 pf note: these values are for design guidance only. since each resonator has its own charac- teristics, the user should consult the reso- nator manufacturer for appropriate values of external components. osc type resonator freq cap.range c1 cap. range c2 lp 32 khz (1) 100 khz 200 khz 15 pf 15-30 pf 15-30 pf 15 pf 30-47 pf 15-82 pf xt 100 khz 200 khz 455 khz 1 mhz 2 mhz 4 mhz 15-30 pf 15-30 pf 15-30 pf 15-30 pf 15-30 pf 15-47 pf 200-300 pf 100-200 pf 15-100 pf 15-30 pf 15-30 pf 15-47 pf hs 4 mhz 8 mhz 20 mhz 15-30 pf 15-30 pf 15-30 pf 15-30 pf 15-30 pf 15-30 pf note 1: for v dd > 4.5v, c1 = c2 30 pf is recommended. 2: these values are for design guidance only. rs may be required in hs mode, as well as xt mode, to avoid overdriving crystals with low drive level specification. since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. note: if you change from one device to another device, please verify oscillator characteris- tics in your application. clock from ext. system osc1 osc2 pic16c5x open
pic16c5x ds30453c-page 34 preliminary ? 2000 microchip technology inc. 7.2.3 external crystal oscillator circuit either a prepackaged oscillator or a simple oscillator circuit with ttl gates can be used as an external crys- tal oscillator circuit. prepackaged oscillators provide a wide operating range and better stability. a well-designed crystal oscillator will provide good perfor- mance with ttl gates. two types of crystal oscillator circuits can be used: one with parallel resonance or one with series resonance. figure 7-5 shows implementation of a parallel resonant oscillator circuit. the circuit is designed to use the fun- damental frequency of the crystal. the 74as04 inverter performs the 180-degree phase shift that a parallel oscillator requires. the 4.7 k ? resistor provides the negative feedback for stability. the 10 k ? potentiome- ters bias the 74as04 in the linear region. this circuit could be used for external oscillator designs. figure 7-5: external parallel resonant crystal oscillator circuit (using xt, hs or lp oscillator mode) this circuit is also designed to use the fundamental fre- quency of the crystal. the inverter performs a 180-degree phase shift in a series resonant oscillator circuit. the 330 ? resistors provide the negative feed- back to bias the inverters in their linear region. note: if you change from one device to another device, please verify oscillator characteris- tics in your application. 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xtal 10k 74as04 pic16c5x osc1 to o t h e r devices osc2 100k figure 7-6: external series resonant crystal oscillator circuit (using xt, hs or lp oscillator mode) 7.2.4 rc oscillator for timing insensitive applications, the rc device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resis- tor (r ext ) and capacitor (c ext ) values, and the operat- ing temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal pro- cess parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c compo- nents used. figure 7-7 shows how the r/c combination is con- nected to the pic16c5x. for r ext values below 2.2 k ? , the oscillator operation may become unstable, or stop completely. for very high r ext values (e.g., 1 m ? ) the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend keeping r ext between 3 k ? and 100 k ? . although the oscillator will operate with no external capacitor (c ext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as pcb trace capacitance or pack- age lead frame capacitance. note: if you change from one device to another device, please verify oscillator characteris- tics in your application. 330 74as04 74as04 pic16c5x osc1 to other devices xtal 330 74as04 0.1 f osc2 100k
? 2000 microchip technology inc. preliminary ds30453c-page 35 pic16c5x the electrical specification sections show rc fre- quency variation from part to part due to normal pro- cess variation. also, see the electrical specification sections for varia- tion of oscillator frequency due to v dd for given r ext /c ext values, as well as frequency variation due to operating temperature for given r, c and v dd val- ues. the oscillator frequency, divided by 4, is available on the osc2/clkout pin, and can be used for test pur- poses or to synchronize other logic. figure 7-7: rc oscillator mode note: if you change from one device to another device, please verify oscillator characteris- tics in your application. v dd r ext c ext v ss osc1 internal clock osc2/clkout f osc /4 pic16c5x n 7.3 reset pic16c5x devices may be reset in one of the follow- ing ways: power-on reset (por) mclr reset (normal operation) mclr wake-up reset (from sleep) wdt reset (normal operation) wdt wake-up reset (from sleep) table 7-3 shows these reset conditions for the pcl and status registers. some registers are not affected in any reset condi- tion. their status is unknown on por and unchanged in any other reset. most other registers are reset to a ? reset state ? on power-on reset (por), mclr or wdt reset. a mclr or wdt wake-up from sleep also results in a device reset, and not a continuation of operation before sleep. the to and pd bits (status <4:3>) are set or cleared depending on the different reset conditions (section 7.7). these bits may be used to determine the nature of the reset. table 7-4 lists a full description of reset states of all registers. figure 7-8 shows a simplified block diagram of the on-chip reset circuit.
pic16c5x ds30453c-page 36 preliminary ? 2000 microchip technology inc. table 7-3: reset conditions for special registers table 7-4: reset conditions for all registers figure 7-8: simplified block diagram of on-chip reset circuit condition pcl addr: 02h status addr: 03h power-on reset 1111 1111 0001 1xxx mclr reset (normal operation) 1111 1111 000u uuuu (1) mclr wake-up (from sleep) 1111 1111 0001 0uuu wdt reset (normal operation) 1111 1111 0000 uuuu (2) wdt wake-up (from sleep) 1111 1111 0000 0uuu legend: u = unchanged, x = unknown, - = unimplemented read as ? 0 ? . note 1: to and pd bits retain their last value until one of the other reset conditions occur. 2: the clrwdt instruction will set the to and pd bits. register address power-on reset mclr or wdt reset wn/a xxxx xxxx uuuu uuuu tris n/a 1111 1111 1111 1111 option n/a --11 1111 --11 1111 indf 00h xxxx xxxx uuuu uuuu tmr0 01h xxxx xxxx uuuu uuuu pcl (1) 02h 1111 1111 1111 1111 status (1) 03h 0001 1xxx 000q quuu fsr 04h 1xxx xxxx 1uuu uuuu porta 05h ---- xxxx ---- uuuu portb 06h xxxx xxxx uuuu uuuu portc (2) 07h xxxx xxxx uuuu uuuu general purpose register files 07-7fh xxxx xxxx uuuu uuuu legend: u = unchanged, x = unknown, - = unimplemented, read as ? 0 ? , q = see tables in section 7.7 for possible values. note 1: see table 7-3 for reset value for specific conditions. 2: general purpose register file on pic16c54/cr54/c56/cr56/c58/cr58. 8-bit asynch ripple counter (start-up timer) sq r q v dd mclr /v pp pin power-up detect on-chip rc osc por (power-on reset) wdt time-out reset chip reset wdt
? 2000 microchip technology inc. preliminary ds30453c-page 37 pic16c5x 7.4 power-on reset (por) the pic16c5x family incorporates on-chip power-on reset (por) circuitry which provides an internal chip reset for most power-up situations. to use this fea- ture, the user merely ties the mclr /v pp pin to v dd . a simplified block diagram of the on-chip power-on reset circuit is shown in figure 7-8. the power-on reset circuit and the device reset timer (section 7.5) circuit are closely related. on power-up, the reset latch is set and the drt is reset. the drt timer begins counting once it detects mclr to be high. after the time-out period, which is typically 18 ms, it will reset the reset latch and thus end the on-chip reset signal. a power-up example where mclr is not tied to v dd is shown in figure 7-10. v dd is allowed to rise and stabi- lize before bringing mclr high. the chip will actually come out of reset t drt msec after mclr goes high. in figure 7-11, the on-chip power-on reset feature is being used (mclr and v dd are tied together). the v dd is stable before the start-up timer times out and there is no problem in getting a proper reset. however, figure 7-12 depicts a problem situation where v dd rises too slowly. the time between when the drt senses a high on the mclr /v pp pin, and when the mclr /v pp pin (and v dd ) actually reach their full value, is too long. in this situation, when the start-up timer times out, v dd has not reached the v dd (min) value and the chip is, therefore, not guaranteed to function cor- rectly. for such situations, we recommend that external (reset) bor circuits or external rc circuits be used to achieve longer por delay times (figure 7-9). for more information on pic16c5x por, see power-up considerations - an522 in the embedded control handbook . the por circuit does not produce an internal reset when v dd declines. note: when the device starts normal operation (exits the reset condition), device oper- ating parameters (voltage, frequency, tem- perature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. figure 7-9: example of external power-on reset circuit (for slow v dd power-up) c r1 r d mclr pic16c5x v dd v dd external power-on reset circuit is required only if v dd power-up is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. r < 40 k ? is recommended to make sure that voltage drop across r does not violate the device electrical specification. r1 = 100 ? to 1 k ? will limit any current flow- ing into mclr from external capacitor c in the event of mclr pin breakdown due to electro- static discharge (esd) or electrical over- stress (eos).
pic16c5x ds30453c-page 38 preliminary ? 2000 microchip technology inc. figure 7-10: time-out sequence on power-up (mclr not tied to v dd ) figure 7-11: time-out sequence on power-up (mclr tied to v dd ): fast v dd rise time figure 7-12: time-out sequence on power-up (mclr tied to v dd ): slow v dd rise time v dd mclr internal por drt time-out internal reset t drt v dd mclr internal por drt time-out internal reset t drt v dd mclr internal por drt time-out internal reset t drt v1 when v dd rises slowly, the t drt time-out expires long before v dd has reached its final value. in this example, the chip will reset properly if, and only if, v1 v dd min.
? 2000 microchip technology inc. preliminary ds30453c-page 39 pic16c5x 7.5 device reset timer (drt) the device reset timer (drt) provides a fixed 18 ms nominal time-out on reset. the drt operates on an internal rc oscillator. the processor is kept in reset as long as the drt is active. the drt delay allows v dd to rise above v dd min., and for the oscillator to stabi- lize. oscillator circuits based on crystals or ceramic resona- tors require a certain time after power-up to establish a stable oscillation. the on-chip drt keeps the device in a reset condition for approximately 18 ms after the voltage on the mclr /v pp pin has reached a logic high (v ih ) level. thus, external rc networks connected to the mclr input are not required in most cases, allow- ing for savings in cost-sensitive and/or space restricted applications. the device reset time delay will vary from device to device due to v dd , temperature, and process variation. see ac parameters for details. the drt will also be triggered upon a watchdog timer time-out. this is particularly important for applications using the wdt to wake the pic16c5x from sleep mode automatically. 7.6 watchdog timer (wdt) the watchdog timer (wdt) is a free running on-chip rc oscillator which does not require any external com- ponents. this rc oscillator is separate from the rc oscillator of the osc1/clkin pin. that means that the wdt will run even if the clock on the osc1/clkin and osc2/clkout pins have been stopped, for example, by execution of a sleep instruction. during normal operation or sleep, a wdt reset or wake-up reset generates a device reset. the to bit (status<4>) will be cleared upon a watch- dog timer reset. the wdt can be permanently disabled by program- ming the configuration bit wdte as a ? 0 ? (section 7.1). refer to the pic16c5x programming specifications (literature number ds30190) to determine how to access the configuration word. 7.6.1 wdt period the wdt has a nominal time-out period of 18 ms (with no prescaler). if a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt (under software control) by writ- ing to the option register. thus, a time-out period of a nominal 2.3 seconds can be realized. these periods vary with temperature, v dd and part-to-part process variations (see dc specs). under worst case conditions (v dd = min., temperature = max., max. wdt prescaler), it may take several sec- onds before a wdt time-out occurs. 7.6.2 wdt programming considerations the clrwdt instruction clears the wdt and the postscaler, if assigned to the wdt, and prevents it from timing out and generating a device reset. the sleep instruction resets the wdt and the postscaler, if assigned to the wdt. this gives the max- imum sleep time before a wdt wake-up reset.
pic16c5x ds30453c-page 40 preliminary ? 2000 microchip technology inc. figure 7-13: watchdog timer block diagram table 7-5: summary of registers associated with the watchdog timer address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on mclr and wdt reset n/a option ? ? t0cs t0se psa ps2 ps1 ps0 --11 1111 --11 1111 legend: shaded boxes = not used by watchdog timer, - = unimplemented, read as '0', u = unchanged 1 0 1 0 from tmr0 clock source to t m r 0 postscaler wdt enable eprom bit psa wdt time-out ps<2:0> psa mux 8 - to - 1 mux postscaler m u x watchdog timer note: t0cs, t0se, psa, ps<2:0> are bits in the option register.
? 2000 microchip technology inc. preliminary ds30453c-page 41 pic16c5x 7.7 time-out sequence and power-down status bits ( to / pd ) the to and pd bits in the status register can be tested to determine if a reset condition has been caused by a power-up condition, a mclr or watchdog timer (wdt) reset, or a mclr or wdt wake-up reset. these status bits are only affected by events listed in table 7-7. table 7-3 lists the reset conditions for the special function registers, while table 7-4 lists the reset conditions for all the registers. table 7-6: to /pd status after reset to pd reset was caused by 11 power-up (por) uu mclr reset (normal operation) (1) 10 mclr wake-up reset (from sleep) 01 wdt reset (normal operation) 00 wdt wake-up reset (from sleep) legend: u = unchanged note 1: the to and pd bits maintain their status ( u ) until a reset occurs. a low-pulse on the mclr input does not change the to and pd status bits. table 7-7: events affecting to /pd status bits event to pd remarks power-up 11 wdt time-out 0u no effect on pd sleep instruction 10 clrwdt instruction 11 legend: u = unchanged note: a wdt time-out will occur regardless of the status of the to bit. a sleep instruc- tion will be executed, regardless of the sta- tus of the pd bit. 7.8 reset on brown-out a brown-out is a condition where device power (v dd ) dips below its minimum value, but not to zero, and then recovers. the device should be reset in the event of a brown-out. to reset pic16c5x devices when a brown-out occurs, external brown-out protection circuits may be built, as shown in figure 7-14 and figure 7-15. figure 7-14: brown-out protection circuit 1 figure 7-15: brown-out protection circuit 2 this circuit will activate reset when v dd goes below vz + 0.7v (where vz = zener voltage). 33k 10k 40k v dd mclr pic16c5x v dd q1 this brown-out circuit is less expensive, although less accurate. transistor q1 turns off when v dd is below a certain level such that: v dd r1 r1 + r2 = 0.7v r2 40k v dd mclr pic16c5x r1 q1 v dd
pic16c5x ds30453c-page 42 preliminary ? 2000 microchip technology inc. figure 7-16: external brown-out protection circuit 3 7.9 power-down mode (sleep) a device may be powered down (sleep) and later powered up (wake-up from sleep). 7.9.1 sleep the power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the to bit (status<4>) is set, the pd bit (status<3>) is cleared and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, driving low, or hi-impedance). it should be noted that a reset generated by a wdt time-out does not drive the mclr /v pp pin low. for lowest current consumption while powered down, the t0cki input should be at v dd or v ss and the mclr /v pp pin must be at a logic high level. 7.9.2 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. an external reset input on mclr /v pp pin. 2. a watchdog timer time-out reset (if wdt was enabled). both of these events cause a device reset. the to and pd bits can be used to determine the cause of device reset. the to bit is cleared if a wdt time-out occurred (and caused wake-up). the pd bit, which is set on power-up, is cleared when sleep is invoked. the wdt is cleared when the device wakes from sleep, regardless of the wake-up source. this brown-out protection circuit employs micro- chip technology ? s mcp809 microcontroller super- visor. the mcp8xx and mcp1xx families of supervisors provide push-pull and open collector outputs with both "active high and active low" reset pins. there are 7 different trip point selec- tions to accommodate 5v and 3v systems. mclr pic16c62x v dd vss rst mcp809 v dd bypass capacitor v dd 7.10 program verification/code protection if the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for verification purposes. 7.11 id locations four memory locations are designated as id locations, where the user can store checksum or other code-identification numbers. these locations are not accessible during normal execution but are readable and writable during program/verify. use only the lower 4 bits of the id locations and always program the upper 8 bits as ? 1 ? s. note: microchip does not recommend code pro- tecting windowed devices. note: microchip will assign a unique pattern number for qtp and sqtp requests and for rom devices. this pattern number will be unique and traceable to the submitted code.
? 2000 microchip technology inc. preliminary ds30453c-page 43 pic16c5x 8.0 instruction set summary each pic16c5x instruction is a 12-bit word divided into an opcode, which specifies the instruction type, and one or more operands which further specify the operation of the instruction. the pic16c5x instruction set summary in table 8-2 groups the instructions into byte-oriented, bit-ori- ented, and literal and control operations. table 8-1 shows the opcode field descriptions. for byte-oriented instructions, ? f ? represents a file register designator and ? d ? represents a destination designator. the file register designator is used to specify which one of the 32 file registers in that bank is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if ? d ? is ? 0 ? , the result is placed in the w register. if ? d ? is ? 1 ? , the result is placed in the file register specified in the instruction. for bit-oriented instructions, ? b ? represents a bit field designator which selects the number of the bit affected by the operation, while ? f ? represents the number of the file in which the bit is located. for literal and control operations, ? k ? represents an 8 or 9-bit constant or literal value. table 8-1: opcode field descriptions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don ? t care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 (store result in w) d = 1 (store result in file register ? f ? ) default is d = 1 label label name tos top of stack pc program counter wdt watchdog timer counter to time-out bit pd power-down bit dest destination, either the w register or the specified register file location [ ] options ( ) contents assigned to < > register bit field in the set of i talics user defined term (font is courier) all instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time would be 1 s. if a condi- tional test is true or the program counter is changed as a result of an instruction, the instruction execution time would be 2 s. figure 8-1 shows the three general formats that the instructions can have. all examples in the figure use the following format to represent a hexadecimal number: 0xhhh where ? h ? signifies a hexadecimal digit. figure 8-1: general format for instructions byte-oriented file register operations 11 6 5 4 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 5-bit file register address bit-oriented file register operations 11 8 7 5 4 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 5-bit file register address literal and control operations (except goto ) 11 8 7 0 opcode k (literal) k = 8-bit immediate value literal and control operations - goto instruction 11 9 8 0 opcode k (literal) k = 9-bit immediate value
pic16c5x ds30453c-page 44 preliminary ? 2000 microchip technology inc. table 8-2: instruction set summary mnemonic, operands description cycles 12-bit opcode status affected notes msb lsb addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f,d f,d f ? f, d f, d f, d f, d f, d f, d f, d f ? f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001 11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z none z none z z none none c c c,dc,z none z 1,2,4 2,4 4 2,4 2,4 2,4 2,4 2,4 2,4 1,4 2,4 2,4 1,2,4 2,4 2,4 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 0100 0101 0110 0111 bbbf bbbf bbbf bbbf ffff ffff ffff ffff none none none none 2,4 2,4 literal and control operations andlw call clrwdt goto iorlw movlw option retlw sleep tris xorlw k k k k k k k k ? f k and literal with w call subroutine clear watchdog timer unconditional branch inclusive or literal with w move literal to w load option register return, place literal in w go into standby mode load tris register exclusive or literal to w 1 2 1 2 1 1 1 2 1 1 1 1110 1001 0000 101k 1101 1100 0000 1000 0000 0000 1111 kkkk kkkk 0000 kkkk kkkk kkkk 0000 kkkk 0000 0000 kkkk kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk z none to , pd none z none none none to , pd none z 1 3 note 1: the 9th bit of the program counter will be forced to a ? 0 ? by any instruction that writes to the pc except for goto . (see individual device data sheets, memory section/indirect data addressing, indf and fsr regis- ters) 2: when an i/o register is modified as a function of itself (e.g. movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ? . 3: the instruction tris f , where f = 5 or 6 causes the contents of the w register to be written to the tristate latches of porta or b respectively. a ? 1 ? forces the pin to a hi-impedance state and disables the output buff- ers. 4: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to tmr0).
? 2000 microchip technology inc. preliminary ds30453c-page 45 pic16c5x addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 31 d [0,1] operation: (w) + (f) (dest) status affected: c, dc, z encoding: 0001 11df ffff description: add the contents of the w register and register ? f ? . if ? d ? is 0 the result is stored in the w register. if ? d ? is ? 1 ? the result is stored back in register ? f ? . words: 1 cycles: 1 example: addwf fsr, 0 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0xd9 fsr = 0xc2 andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w).and. (k) (w) status affected: z encoding: 1110 kkkk kkkk description: the contents of the w register are and ? ed with the eight-bit literal 'k'. the result is placed in the w register . words: 1 cycles: 1 example: andlw 0x5f before instruction w= 0xa3 after instruction w = 0x03 andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 31 d [0,1] operation: (w) .and. (f) (dest) status affected: z encoding: 0001 01df ffff description: the contents of the w register are and ? ed with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is '1' the result is stored back in register 'f' . words: 1 cycles: 1 example: andwf fsr, 1 before instruction w =0x17 temp_reg = 0xc2 after instruction w =0x17 temp_reg = 0x2 bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 31 0 b 7 operation: 0 (f) status affected: none encoding: 0100 bbbf ffff description: bit 'b' in register 'f' is cleared. words: 1 cycles: 1 example: bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47
pic16c5x ds30453c-page 46 preliminary ? 2000 microchip technology inc. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 31 0 b 7 operation: 1 (f) status affected: none encoding: 0101 bbbf ffff description: bit ? b ? in register ? f ? is set. words: 1 cycles: 1 example: bsf flag_reg, 7 before instruction flag_reg = 0x0a after instruction flag_reg = 0x8a btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 31 0 b 7 operation: skip if (f) = 0 status affected: none encoding: 0110 bbbf ffff description: if bit ? b ? in register ? f ? is 0 then the next instruction is skipped. if bit ? b ? is 0 then the next instruction fetched during the current instruction execution is discarded, and a nop is executed instead, making this a 2-cycle instruction. words: 1 cycles: 1(2) example: here false true btfsc goto flag,1 process_code before instruction pc = address (here) after instruction if flag<1> = 0, pc = address (true) ; if flag<1> = 1, pc = address (false) btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 31 0 b < 7 operation: skip if (f) = 1 status affected: none encoding: 0111 bbbf ffff description: if bit ? b ? in register ? f ? is ? 1 ? then the next instruction is skipped. if bit ? b ? is ? 1 ? , then the next instruction fetched during the current instruction execution, is discarded and a nop is executed instead, making this a 2-cycle instruction. words: 1 cycles: 1(2) example: here btfss flag,1 false goto process_code true ? ? ? before instruction pc = address (here) after instruction if flag<1> = 0, pc = address (false) ; if flag<1> = 1, pc = address (true)
? 2000 microchip technology inc. preliminary ds30453c-page 47 pic16c5x call subroutine call syntax: [ label ] call k operands: 0 k 255 operation: (pc) + 1 top of stack; k pc<7:0>; (status<6:5>) pc<10:9>; 0 pc<8> status affected: none encoding: 1001 kkkk kkkk description: subroutine call. first, return address (pc+1) is pushed onto the stack. the eight bit immediate address is loaded into pc bits <7:0>. the upper bits pc<10:9> are loaded from status<6:5>, pc<8> is cleared. call is a two-cycle instruction. words: 1 cycles: 2 example: here call there before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 1) clrf clear f syntax: [ label ] clrf f operands: 0 f 31 operation: 00h (f); 1 z status affected: z encoding: 0000 011f ffff description: the contents of register ? f ? are cleared and the z bit is set. words: 1 cycles: 1 example: clrf flag_reg before instruction flag_reg = 0x5a after instruction flag_reg = 0x00 z=1 clrw clear w syntax: [ label ] clrw operands: none operation: 00h (w); 1 z status affected: z encoding: 0000 0100 0000 description: the w register is cleared. zero bit (z) is set. words: 1 cycles: 1 example: clrw before instruction w = 0x5a after instruction w = 0x00 z=1 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h wdt; 0 wdt prescaler (if assigned); 1 to; 1 pd status affected: to , pd encoding: 0000 0000 0100 description: the clrwdt instruction resets the wdt. it also resets the prescaler, if the prescaler is assigned to the wdt and not timer0. status bits to and pd are set. words: 1 cycles: 1 example: clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt prescale = 0 to =1 pd =1
pic16c5x ds30453c-page 48 preliminary ? 2000 microchip technology inc. comf complement f syntax: [ label ] comf f,d operands: 0 f 31 d [0,1] operation: (f ) (dest) status affected: z encoding: 0010 01df ffff description: the contents of register ? f ? are comple- mented. if ? d ? is 0 the result is stored in the w register. if ? d ? is 1 the result is stored back in register ? f ? . words: 1 cycles: 1 example: comf reg1,0 before instruction reg1 = 0x13 after instruction reg1 = 0x13 w=0xec decf decrement f syntax: [ label ] decf f,d operands: 0 f 31 d [0,1] operation: (f) ? 1 (dest) status affected: z encoding: 0000 11df ffff description: decrement register ? f ? . if ? d ? is 0 the result is stored in the w register. if ? d ? is 1 the result is stored back in register ? f ? . words: 1 cycles: 1 example: decf cnt, 1 before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 31 d [0,1] operation: (f) ? 1 d; skip if result = 0 status affected: none encoding: 0010 11df ffff description: the contents of register ? f ? are decre- mented. if ? d ? is 0 the result is placed in the w register. if ? d ? is 1 the result is placed back in register ? f ? . if the result is 0, the next instruction, which is already fetched, is discarded and a nop is executed instead making it a two-cycle instruction. words: 1 cycles: 1(2) example: here decfsz cnt, 1 goto loop continue before instruction pc = address (here) after instruction cnt = cnt - 1; if cnt = 0, pc = address (continue) ; if cnt 0, pc = address (here+1) goto unconditional branch syntax: [ label ] goto k operands: 0 k 511 operation: k pc<8:0>; status<6:5> pc<10:9> status affected: none encoding: 101k kkkk kkkk description: goto is an unconditional branch. the 9-bit immediate value is loaded into pc bits <8:0>. the upper bits of pc are loaded from status<6:5>. goto is a two-cycle instruction. words: 1 cycles: 2 example: goto there after instruction pc = address (there)
? 2000 microchip technology inc. preliminary ds30453c-page 49 pic16c5x incf increment f syntax: [ label ] incf f,d operands: 0 f 31 d [0,1] operation: (f) + 1 (dest) status affected: z encoding: 0010 10df ffff description: the contents of register ? f ? are incre- mented. if ? d ? is 0 the result is placed in the w register. if ? d ? is 1 the result is placed back in register ? f ? . words: 1 cycles: 1 example: incf cnt, 1 before instruction cnt = 0xff z=0 after instruction cnt = 0x00 z=1 incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 31 d [0,1] operation: (f) + 1 (dest), skip if result = 0 status affected: none encoding: 0011 11df ffff description: the contents of register ? f ? are incre- mented. if ? d ? is 0 the result is placed in the w register. if ? d ? is 1 the result is placed back in register ? f ? . if the result is 0, then the next instruc- tion, which is already fetched, is dis- carded and a nop is executed instead making it a two-cycle instruction. words: 1 cycles: 1(2) example: here incfsz cnt, 1 goto loop continue before instruction pc = address (here) after instruction cnt = cnt + 1; if cnt = 0, pc = address (continue) ; if cnt 0, pc = address (here +1) iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. (k) (w) status affected: z encoding: 1101 kkkk kkkk description: the contents of the w register are or ? ed with the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example: iorlw 0x35 before instruction w = 0x9a after instruction w= 0xbf z=0 iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 31 d [0,1] operation: (w).or. (f) (dest) status affected: z encoding: 0001 00df ffff description: inclusive or the w register with regis- ter 'f'. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example: iorwf result, 0 before instruction result = 0x13 w = 0x91 after instruction result = 0x13 w = 0x93 z=0
pic16c5x ds30453c-page 50 preliminary ? 2000 microchip technology inc. movf move f syntax: [ label ] movf f,d operands: 0 f 31 d [0,1] operation: (f) (dest) status affected: z encoding: 0010 00df ffff description: the contents of register ? f ? is moved to destination ? d ? . if ? d ? is 0, destination is the w register. if ? d ? is 1, the destination is file register ? f ? . ? d ? is 1 is useful to test a file register since status flag z is affected. words: 1 cycles: 1 example: movf fsr, 0 after instruction w = value in fsr register movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k (w) status affected: none encoding: 1100 kkkk kkkk description: the eight bit literal ? k ? is loaded into the w register. the don ? t cares will assem- ble as 0s. words: 1 cycles: 1 example: movlw 0x5a after instruction w = 0x5a movwf move w to f syntax: [ label ] movwf f operands: 0 f 31 operation: (w) (f) status affected: none encoding: 0000 001f ffff description: move data from the w register to regis- ter 'f' . words: 1 cycles: 1 example: movwf temp_reg before instruction temp_reg = 0xff w = 0x4f after instruction temp_reg = 0x4f w = 0x4f nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 0000 0000 0000 description: no operation. words: 1 cycles: 1 example: nop
? 2000 microchip technology inc. preliminary ds30453c-page 51 pic16c5x option load option register syntax: [ label ] option operands: none operation: (w) option status affected: none encoding: 0000 0000 0010 description: the content of the w register is loaded into the option register. words: 1 cycles: 1 example option before instruction w = 0x07 after instruction option = 0x07 retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k (w); tos pc status affected: none encoding: 1000 kkkk kkkk description: the w register is loaded with the eight bit literal ? k ? . the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. words: 1 cycles: 2 example: table call table ;w contains ;table offset ;value. ;w now has table ;value. addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; retlw kn ; end of table before instruction w = 0x07 after instruction w = value of k8 rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 31 d [0,1] operation: see description below status affected: c encoding: 0011 01df ffff description: the contents of register ? f ? are rotated one bit to the left through the carry flag. if ? d ? is 0 the result is placed in the w register. if ? d ? is 1 the result is stored back in register ? f ? . words: 1 cycles: 1 example: rlf reg1,0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 w= 1100 1100 c= 1 rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 31 d [0,1] operation: see description below status affected: c encoding: 0011 00df ffff description: the contents of register ? f ? are rotated one bit to the right through the carry flag. if ? d ? is 0 the result is placed in the w register. if ? d ? is 1 the result is placed back in register ? f ? . words: 1 cycles: 1 example: rrf reg1,0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 w= 0111 0011 c= 0 c register ? f ? c register ? f ?
pic16c5x ds30453c-page 52 preliminary ? 2000 microchip technology inc. sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h wdt; 0 wdt prescaler; 1 to ; 0 pd status affected: to , pd encoding: 0000 0000 0011 description: time-out status bit (to ) is set. the power-down status bit (pd ) is cleared. the wdt and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. see sec- tion on sleep for more details. words: 1 cycles: 1 example: sleep subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 31 d [0,1] operation: (f) ? (w) ( dest) status affected: c, dc, z encoding: 0000 10df ffff description: subtract (2 ? s complement method) the w register from register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example 1 : subwf reg1, 1 before instruction reg1 = 3 w=2 c=? after instruction reg1 = 1 w=2 c = 1 ; result is positive example 2 : before instruction reg1 = 2 w=2 c=? after instruction reg1 = 0 w=2 c = 1 ; result is zero example 3 : before instruction reg1 = 1 w=2 c=? after instruction reg1 = ff w=2 c = 0 ; result is negative
? 2000 microchip technology inc. preliminary ds30453c-page 53 pic16c5x swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 31 d [0,1] operation: (f<3:0>) (dest<7:4>); (f<7:4>) (dest<3:0>) status affected: none encoding: 0011 10df ffff description: the upper and lower nibbles of register ? f ? are exchanged. if ? d ? is 0 the result is placed in w register. if ? d ? is 1 the result is placed in register ? f ? . words: 1 cycles: 1 example swapf reg1, 0 before instruction reg1 = 0xa5 after instruction reg1 = 0xa5 w = 0x5a tris load tris register syntax: [ label ] tris f operands: f = 5, 6 or 7 operation: (w) tris register f status affected: none encoding: 0000 0000 0fff description: tris register ? f ? (f = 5, 6, or 7) is loaded with the contents of the w register. words: 1 cycles: 1 example tris porta before instruction w=0xa5 after instruction trisa = 0xa5 xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 k 255 operation: (w) .xor. k ( w) status affected: z encoding: 1111 kkkk kkkk description: the contents of the w register are xor ? ed with the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example: xorlw 0xaf before instruction w= 0xb5 after instruction w = 0x1a xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 31 d [0,1] operation: (w) .xor. (f) ( dest) status affected: z encoding: 0001 10df ffff description: exclusive or the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example xorwf reg,1 before instruction reg = 0xaf w=0xb5 after instruction reg = 0x1a w=0xb5
pic16c5x ds30453c-page 54 preliminary ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. preliminary ds30453c-page 55 pic16c5x 9.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: integrated development environment - mplab ? ide software assemblers/compilers/linkers - mpasm assembler - mplab-c17 and mplab-c18 c compilers - mplink/mplib linker/librarian simulators - mplab-sim software simulator emulators - mplab-ice real-time in-circuit emulator - icepic ? in-circuit debugger - mplab-icd for pic16f87 device programmers -pro mate ? ii universal programmer - picstart ? plus entry-level prototype programmer low-cost demonstration boards - picdem-1 - picdem-2 - picdem-3 - picdem-17 -k ee l oq ? 9.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. mplab is a windows ? -based applica- tion which contains: multiple functionality -editor - simulator - programmer (sold separately) - emulator (sold separately) a full featured editor a project manager customizable tool bar and key mapping a status bar on-line help mplab allows you to: edit your source files (either assembly or ? c ? ) one touch assemble (or compile) and download to picmicro tools (automatically updates all project information) debug using: - source files - absolute listing file - object code the ability to use mplab with microchip ? s simulator, mplab-sim, allows a consistent platform and the abil- ity to easily switch from the cost-effective simulator to the full featured emulator with minimal retraining. 9.2 mpasm assembler mpasm is a full featured universal macro assembler for all picmicro mcu ? s. it can produce absolute code directly in the form of hex files for device program- mers, or it can generate relocatable objects for mplink. mpasm has a command line interface and a windows shell and can be used as a standalone application on a windows 3.x or greater system. mpasm generates relocatable object files, intel standard hex files, map files to detail memory usage and symbol reference, an absolute lst file which contains source lines and gen- erated machine code, and a cod file for mplab debugging. mpasm features include: mpasm and mplink are integrated into mplab projects. mpasm allows user defined macros to be created for streamlined assembly. mpasm allows conditional assembly for multi pur- pose source files. mpasm directives allow complete control over the assembly process. 9.3 mplab-c17 and mplab-c18 c compilers the mplab-c17 and mplab-c18 code development systems are complete ansi ? c ? compilers and inte- grated development environments for microchip ? s pic17cxxx and pic18cxxx family of microcontrol- lers, respectively. these compilers provide powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compilers pro- vide symbol information that is compatible with the mplab ide memory display.
pic16c5x ds30453c-page 56 preliminary ? 2000 microchip technology inc. 9.4 mplink/mplib linker/librarian mplink is a relocatable linker for mpasm and mplab-c17 and mplab-c18. it can link relocatable objects from assembly or c source files along with pre- compiled libraries using directives from a linker script. mplib is a librarian for pre-compiled code to be used with mplink. when a routine from a library is called from another source file, only the modules that contains that routine will be linked in with the application. this allows large libraries to be used efficiently in many dif- ferent applications. mplib manages the creation and modification of library files. mplink features include: mplink works with mpasm and mplab-c17 and mplab-c18. mplink allows all memory areas to be defined as sections to provide link-time flexibility. mplib features include: mplib makes linking easier because single librar- ies can be included instead of many smaller files. mplib helps keep code maintainable by grouping related modules together. mplib commands allow libraries to be created and modules to be added, listed, replaced, deleted, or extracted. 9.5 mplab-sim software simulator the mplab-sim software simulator allows code development in a pc host environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file or user-defined key press to any of the pins. the execution can be performed in single step, execute until break, or trace mode. mplab-sim fully supports symbolic debugging using mplab-c17 and mplab-c18 and mpasm. the soft- ware simulator offers the flexibility to develop and debug code outside of the laboratory environment mak- ing it an excellent multi-project software development tool. 9.6 mplab-ice high performance universal in-circuit emulator with mplab ide the mplab-ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers (mcus). software control of mplab-ice is provided by the mplab integrated development environment (ide), which allows editing, ? make ? and download, and source debugging from a single environment. interchangeable processor modules allow the system to be easily reconfigured for emulation of different pro- cessors. the universal architecture of the mplab-ice allows expansion to support new picmicro microcon- trollers. the mplab-ice emulator system has been designed as a real-time emulation system with advanced fea- tures that are generally found on more expensive devel- opment tools. the pc platform and microsoft ? windows 3.x/95/98 environment were chosen to best make these features available to you, the end user. mplab-ice 2000 is a full-featured emulator system with enhanced trace, trigger, and data monitoring fea- tures. both systems use the same processor modules and will operate across the full operating speed range of the picmicro mcu. 9.7 icepic icepic is a low-cost in-circuit emulation solution for the microchip technology pic16c5x, pic16c6x, pic16c7x, and pic16cxxx families of 8-bit one-time- programmable (otp) microcontrollers. the modular system can support different subsets of pic16c5x or pic16cxxx products through the use of interchange- able personality modules or daughter boards. the emulator is capable of emulating without target applica- tion circuitry being present. 9.8 mplab-icd in-circuit debugger microchip ? s in-circuit debugger, mplab-icd, is a pow- erful, low-cost run-time development tool. this tool is based on the flash pic16f877 and can be used to develop for this and other picmicro microcontrollers from the pic16cxxx family. mplab-icd utilizes the in-circuit debugging capability built into the pic16f87x. this feature, along with microchip ? s in-cir- cuit serial programming protocol, offers cost-effective in-circuit flash programming and debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. running at full speed enables testing hardware in real-time. the mplab-icd is also a programmer for the flash pic16f87x family.
? 2000 microchip technology inc. preliminary ds30453c-page 57 pic16c5x 9.9 pro mate ii universal programmer the pro mate ii universal programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as pc-hosted mode. pro mate ii is ce compliant. the pro mate ii has programmable v dd and v pp supplies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand-alone mode the pro mate ii can read, verify or program picmicro devices. it can also set code-protect bits in this mode. 9.10 picstart plus entry level development system the picstart programmer is an easy-to-use, low- cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. mplab integrated development environment software makes using the programmer simple and efficient. picstart plus supports all picmicro devices with up to 40 pins. larger pin count devices such as the pic16c92x, and pic17c76x may be supported with an adapter socket. picstart plus is ce compliant. 9.11 picdem-1 low-cost picmicro demonstration board the picdem-1 is a simple board which demonstrates the capabilities of several of microchip ? s microcontrol- lers. the microcontrollers supported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the users can program the sample microcontrollers provided with the picdem-1 board, on a pro mate ii or picstart-plus programmer, and easily test firm- ware. the user can also connect the picdem-1 board to the mplab-ice emulator and download the firmware to the emulator for testing. additional proto- type area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simulated analog input, push-button switches and eight leds connected to portb. 9.12 picdem-2 low-cost pic16cxx demonstration board the picdem-2 is a simple demonstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers provided with the picdem-2 board, on a pro mate ii pro- grammer or picstart-plus, and easily test firmware. the mplab-ice emulator may also be used with the picdem-2 board to test firmware. additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a serial eeprom to demonstrate usage of the i 2 c bus and separate headers for connec- tion to an lcd module and a keypad. 9.13 picdem-3 low-cost pic16cxxx demonstration board the picdem-3 is a simple demonstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with a lcd module. all the neces- sary hardware and software is included to run the basic demonstration programs. the user can pro- gram the sample microcontrollers provided with the picdem-3 board, on a pro mate ii program- mer or picstart plus with an adapter socket, and easily test firmware. the mplab-ice emulator may also be used with the picdem-3 board to test firm- ware. additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include an rs-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem-3 board is an lcd panel, with 4 commons and 12 seg- ments, that is capable of displaying time, temperature and day of the week. the picdem-3 provides an addi- tional rs-232 interface and windows 3.1 software for showing the demultiplexed lcd signals on a pc. a sim- ple serial interface allows the user to construct a hard- ware demultiplexer for the lcd signals.
pic16c5x ds30453c-page 58 preliminary ? 2000 microchip technology inc. 9.14 picdem-17 the picdem-17 is an evaluation board that demon- strates the capabilities of several microchip microcon- trollers, including pic17c752, pic17c756, pic17c762, and pic17c766. all necessary hardware is included to run basic demo programs, which are sup- plied on a 3.5-inch disk. a programmed sample is included, and the user may erase it and program it with the other sample programs using the pro mate ii or picstart plus device programmers and easily debug and test the sample code. in addition, picdem-17 sup- ports down-loading of programs to and executing out of external flash memory on board. the picdem-17 is also usable with the mplab-ice or picmaster emu- lator, and all of the sample programs can be run and modified using either emulator. additionally, a gener- ous prototype area is available for user hardware. 9.15 k ee l oq evaluation and programming tools k ee l oq evaluation and programming tools support microchips hcs secure data products. the hcs eval- uation kit includes an lcd display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters.
? 2000 microchip technology inc. preliminary ds30453c-page 59 pic16c5x table 9-1: development tools from microchip pic12cxxx pic14000 pic16c5x pic16c6x pic16cxxx pic16f62x pic16c7x pic16c7xx pic16c8x pic16f8xx pic16c9xx pic17c4x pic17c7xx pic18cxx2 24cxx/ 25cxx/ 93cxx hcsxxx mcrfxxx mcp2510 software tools mplab ? integrated development environment mplab ? c17 compiler mplab ? c18 compiler mpasm/mplink emulators mplab ? -ice ** icepic ? low-cost in-circuit emulator debugger mplab ? -icd in-circuit debugger * * programmers picstart ? plus low-cost universal dev. kit ** pro mate ? ii universal programmer ** demo boards and eval kits picdem-1 ? picdem-2 ? ? picdem-3 picdem-14a picdem-17 k ee l oq ? evaluation kit k ee l oq transponder kit microid ? programmer ? s kit 125 khz microid developer ? s kit 125 khz anticollision microid developer ? s kit 13.56 mhz anticollision microid developer ? s kit mcp2510 can developer ? s kit * contact the microchip technology inc. web site at www.microchip.com for information on how to use the mplab ? -icd in-circuit debugger (dv164001) with pic16c62, 63, 64, 65, 72, 73, 74, 76, 77 ** contact microchip technology inc. for availability date. ? development tool is available on select devices.
pic16c5x ds30453c-page 60 preliminary ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. preliminary ds30453c-page 61 pic16c54/55/56/57 pic16c5x 10.0 electrical characteristics - pic16c54/55/56/57 absolute maximum ratings ? ambient temperature under bias ................................................................................................. .......... ? 55 c to +125 c storage temperature ............................................................................................................ ................. ? 65 c to +150 c voltage on v dd with respect to v ss ............................................................................................................... 0v to +7.5v voltage on mclr with respect to v ss (2) ......................................................................................................... 0v to +14v voltage on all other pins with respect to v ss ................................................................................. ? 0.6v to (v dd + 0.6v) total power dissipation (1) ............................................................................................................................... .....800 mw max. current out of v ss pin ........................................................................................................................... .......150 ma max. current into v dd pin ........................................................................................................................... ..........100 ma max. current into an input pin (t0cki only) .................................................................................................................... 500 a input clamp current, i ik (v i < 0 or v i > v dd ) .................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................ 20 ma max. output current sunk by any i/o pin........................................................................................ ........................25 ma max. output current sourced by any i/o pin..................................................................................... ......................20 ma max. output current sourced by a single i/o port (porta, b or c)............................................................... ........40 ma max. output current sunk by a single i/o port (porta, b or c) .................................................................. ..........50 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd ? i oh } + {(v dd ? v oh ) x i oh } + (v ol x i ol ) 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50 to 100 ? should be used when applying a ? low ? level to the mclr pin rather than pulling this pin directly to v ss . ? notice: stresses above those listed under ? maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16c5x pic16c54/55/56/57 ds30453c-page 62 preliminary ? 2000 microchip technology inc. 10.1 dc characteristics: pic16c54/55/56/57-rc, xt, 10, hs, lp (commercial ) dc characteristics power supply pins standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c characteristic sym min typ (1) max units conditions supply voltage pic16c5x-rc pic16c5x-xt pic16c5x-10 pic16c5x-hs pic16c5x-lp v dd 3.0 3.0 4.5 4.5 2.5 ? ? ? ? ? ? 6.25 6.25 5.5 5.5 6.25 v v v v v f osc = dc to 4 mhz f osc = dc to 4 mhz f osc = dc to 10 mhz f osc = dc to 20 mhz f osc = dc to 40 khz ram data retention voltage (2) v dr 1.5* ? v device in sleep mode v dd start voltage to ensure power-on reset v por v ss ? v see section 7.4 for details on power-on reset v dd rise rate to ensure power-on reset s vdd 0.05* ?? v/ms see section 7.4 for details on power-on reset supply current (3) pic16c5x-rc (4) pic16c5x-xt pic16c5x-10 pic16c5x-hs pic16c5x-lp i dd ? ? ? ? ? ? ? 1.8 1.8 4.8 4.8 9.0 15 3.3 3.3 10 10 20 32 ma ma ma ma ma a f osc = 4 mhz, v dd = 5.5v f osc = 4 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 20 mhz, v dd = 5.5v f osc = 32 khz, v dd = 3.0v, wdt disabled power-down current (5) i pd ? ? 4.0 0.6 12 9 a a v dd = 3.0v, wdt enabled v dd = 3.0v, wdt disabled * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? . 5: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss .
? 2000 microchip technology inc. preliminary ds30453c-page 63 pic16c54/55/56/57 pic16c5x 10.2 dc characteristics: pic16c54/55/56/57-rci, xti, 10i, hsi, lpi (industrial ) dc characteristics power supply pins standard operating conditions (unless otherwise specified) operating temperature ? 40 c t a +85 c characteristic sym min typ (1) max units conditions supply voltage pic16c5x-rci pic16c5x-xti pic16c5x-10i pic16c5x-hsi pic16c5x-lpi v dd 3.0 3.0 4.5 4.5 2.5 ? ? ? ? ? 6.25 6.25 5.5 5.5 6.25 v v v v v f osc = dc to 4 mhz f osc = dc to 4 mhz f osc = dc to 10 mhz f osc = dc to 20 mhz f osc = dc to 40 khz ram data retention voltage (2) v dr ? 1.5* ? v device in sleep mode v dd start voltage to ensure power-on reset v por ? v ss ? v see section 7.4 for details on power-on reset v dd rise rate to ensure power-on reset s vdd 0.05* ?? v/ms see section 7.4 for details on power-on reset supply current (3) pic16c5x-rci (4) pic16c5x-xti pic16c5x-10i pic16c5x-hsi pic16c5x-lpi i dd ? ? ? ? ? ? 1.8 1.8 4.8 4.8 9.0 15 3.3 3.3 10 10 20 40 ma ma ma ma ma a f osc = 4 mhz, v dd = 5.5v f osc = 4 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 20 mhz, v dd = 5.5v f osc = 32 khz, v dd = 3.0v, wdt disabled power-down current (5) i pd ? ? 4.0 0.6 14 12 a a v dd = 3.0v, wdt enabled v dd = 3.0v, wdt disabled * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? . 5: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss .
pic16c5x pic16c54/55/56/57 ds30453c-page 64 preliminary ? 2000 microchip technology inc. 10.3 dc characteristics: pic16c54/55/56/57-rce, xte, 10e, hse, lpe (extended) dc characteristics power supply pins standard operating conditions (unless otherwise specified) operating temperature ? 40 c t a +125 c characteristic sym min typ (1) max units conditions supply voltage pic16c5x-rce pic16c5x-xte pic16c5x-10e pic16c5x-hse pic16c5x-lpe v dd 3.25 3.25 4.5 4.5 2.5 ? ? ? ? ? 6.0 6.0 5.5 5.5 6.0 v v v v v f osc = dc to 4 mhz f osc = dc to 4 mhz f osc = dc to 10 mhz f osc = dc to 16 mhz f osc = dc to 40 khz ram data retention voltage (2) v dr ? 1.5* ? v device in sleep mode v dd start voltage to ensure power-on reset v por ? v ss ? v see section 7.4 for details on power-on reset v dd rise rate to ensure power-on reset s vdd 0.05* ?? v/ms see section 7.4 for details on power-on reset supply current (3) pic16c5x-rce (4) pic16c5x-xte pic16c5x-10e pic16c5x-hse pic16c5x-lpe i dd ? ? ? ? ? ? 1.8 1.8 4.8 4.8 9.0 19 3.3 3.3 10 10 20 55 ma ma ma ma ma a f osc = 4 mhz, v dd = 5.5v f osc = 4 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 16 mhz, v dd = 5.5v f osc = 32 khz, v dd = 3.25v, wdt disabled power-down current (5) i pd ? ? 5.0 0.8 22 18 a a v dd = 3.25v, wdt enabled v dd = 3.25v, wdt disabled * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? . 5: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss .
? 2000 microchip technology inc. preliminary ds30453c-page 65 pic16c54/55/56/57 pic16c5x 10.4 dc characteristics: pic16c54/55/56/57-rc, xt, 10, hs, lp (commercial) pic16c54/55/56/57-rci, xti, 10i, hsi, lpi (industrial) dc characteristics all pins except power supply pins standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) operating voltage v dd range is described in section 10.1, section 10.2 and section 10.3. characteristic sym min typ (1) max units conditions input low voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) v il v ss v ss v ss v ss v ss ? ? ? ? ? 0.2 v dd 0.15 v dd 0.15 v dd 0.15 v dd 0.3 v dd v v v v v pin at hi-impedance pic16c5x-rc only (4) pic16c5x-xt, 10, hs, lp input high voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) v ih 0.45 v dd 2.0 0.36 v dd 0.85 v dd 0.85 v dd 0.85 v dd 0.7 v dd ? ? ? ? ? ? ? v dd v dd v dd v dd v dd v dd v dd v v v v v v v for all v dd (5) 4.0v < v dd 5.5v (5) v dd > 5.5v pic16c5x-rc only (4) pic16c5x-xt, 10, hs, lp hysteresis of schmitt trigger inputs v hys 0.15v dd * ?? v input leakage current (2,3) i/o ports mclr t0cki osc1 i il ? 1 ? 5 ? 3 ? 3 0.5 0.5 0.5 0.5 +1 +5 +3 +3 a a a a a for v dd 5.5v v ss v pin v dd , pin at hi-impedance v pin = v ss + 0.25v v pin = v dd v ss v pin v dd v ss v pin v dd , pic16c5x-xt, 10, hs, lp output low voltage i/o ports osc2/clkout v ol ? ? ? ? 0.6 0.6 v v i ol = 8.7 ma, v dd = 4.5v i ol = 1.6 ma, v dd = 4.5v, pic16c5x-rc output high voltage i/o ports (3) osc2/clkout v oh v dd ? 0.7 v dd ? 0.7 ? ? ? ? v v i oh = ? 5.4 ma, v dd = 4.5v i oh = ? 1.0 ma, v dd = 4.5v, pic16c5x-rc * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input volt- age. 3: negative current is defined as coming out of the pin. 4: for pic16c5x-rc devices, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c5x be driven with external clock in rc mode. 5: the user may use the better of the two specifications.
pic16c5x pic16c54/55/56/57 ds30453c-page 66 preliminary ? 2000 microchip technology inc. 10.5 dc characteristics: pic16c54/55/56/57-rc, xt, 10, hs, lp (extended) dc characteristics all pins except power supply pins standard operating conditions (unless otherwise specified) operating temperature ? 40 c t a +125 c operating voltage v dd range is described in section 10.1, section 10.2 and section 10.3. characteristic sym min typ (1) max units conditions input low voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) v il vss vss vss vss vss ? ? ? ? ? 0.15 v dd 0.15 v dd 0.15 v dd 0.15 v dd 0.3 v dd v v v v v pin at hi-impedance pic16c5x-rc only (4) pic16c5x-xt, 10, hs, lp input high voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) v ih 0.45 v dd 2.0 0.36 v dd 0.85 v dd 0.85 v dd 0.85 v dd 0.7 v dd ? ? ? ? ? ? ? v dd v dd v dd v dd v dd v dd v dd v v v v v v v for all v dd (5) 4.0v < v dd 5.5v (5) v dd > 5.5 v pic16c5x-rc only (4) pic16c5x-xt, 10, hs, lp hysteresis of schmitt trigger inputs v hys 0.15v dd * ?? v input leakage current (2,3) i/o ports mclr t0cki osc1 i il ? 1 ? 5 ? 3 ? 3 0.5 0.5 0.5 0.5 +1 +5 +3 +3 a a a a a for v dd 5.5 v v ss v pin v dd , pin at hi-impedance v pin = v ss + 0.25v v pin = v dd v ss v pin v dd v ss v pin v dd , pic16c5x-xt, 10, hs, lp output low voltage i/o ports osc2/clkout v ol ? ? ? ? 0.6 0.6 v v i ol = 8.7 ma, v dd = 4.5v i ol = 1.6 ma, v dd = 4.5v, pic16c5x-rc output high voltage i/o ports (3) osc2/clkout v oh v dd ? 0.7 v dd ? 0.7 ? ? ? ? v v i oh = ? 5.4 ma, v dd = 4.5v i oh = ? 1.0 ma, v dd = 4.5v, pic16c5x-rc * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltage. 3: negative current is defined as coming out of the pin. 4: for pic16c5x-rc devices, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c5x be driven with external clock in rc mode. 5: the user may use the better of the two specifications.
? 2000 microchip technology inc. preliminary ds30453c-page 67 pic16c54/55/56/57 pic16c5x 10.6 timing parameter symbology and load conditions the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 2. tpps t f frequency t time lowercase subscripts (pp) and their meanings: pp 2to mcmclr ck clkout osc oscillator cy cycle time os osc1 drt device reset timer t0 t0cki io i/o port wdt watchdog timer uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance figure 10-1: load conditions - pic16c54/55/56/57 c l v ss pin c l = 50 pf for all pins except osc2 15 pf for osc2 in xt, hs or lp modes when external clock is used to drive osc1
pic16c5x pic16c54/55/56/57 ds30453c-page 68 preliminary ? 2000 microchip technology inc. 10.7 timing diagrams and specifications figure 10-2: external clock timing - pic16c54/55/56/57 table 10-1: external clock timing requirements - pic16c54/55/56/57 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 10.1, section 10.2 and section 10.3 parameter no. sym characteristic min typ (1) max units conditions f osc external clkin frequency (2) dc ? 4mhzxt osc mode dc ? 10 mhz 10 mhz mode dc ? 20 mhz hs osc mode (com/indust) dc ? 16 mhz hs osc mode (extended) dc ? 40 khz lp osc mode oscillator frequency (2) dc ? 4 mhz rc osc mode 0.1 ? 4mhzxt osc mode 4 ? 10 mhz 10 mhz mode 4 ? 20 mhz hs osc mode (com/indust) 4 ? 16 mhz hs osc mode (extended) dc ? 40 khz lp osc mode * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: all specified values are based on characterization data for that particular oscillator type under standard oper- ating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ? max ? cycle time limit is ? dc ? (no clock) for all devices. 3: instruction cycle period (t cy ) equals four times the input oscillator time base period. osc1 clkout q4 q1 q2 q3 q4 q1 133 44 2
? 2000 microchip technology inc. preliminary ds30453c-page 69 pic16c54/55/56/57 pic16c5x 1t osc external clkin period (2) 250 ?? ns xt osc mode 100 ?? ns 10 mhz mode 50 ?? ns hs osc mode (com/indust) 62.5 ?? ns hs osc mode (extended) 25 ?? slp osc mode oscillator period (2) 250 ?? ns rc osc mode 250 ? 10,000 ns xt osc mode 100 ? 250 ns 10 mhz mode 50 ? 250 ns hs osc mode (com/indust) 62.5 ? 250 ns hs osc mode (extended) 25 ?? slp osc mode 2t cy instruction cycle time (3) ? 4/f osc ?? 3 tosl, tosh clock in (osc1) low or high time 85* ?? ns xt oscillator 20* ?? ns hs oscillator 2* ?? s lp oscillator 4 tosr, tosf clock in (osc1) rise or fall time ?? 25* ns xt oscillator ?? 25* ns hs oscillator ?? 50* ns lp oscillator table 10-1: external clock timing requirements - pic16c54/55/56/57 (con ? t) ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 10.1, section 10.2 and section 10.3 parameter no. sym characteristic min typ (1) max units conditions * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: all specified values are based on characterization data for that particular oscillator type under standard oper- ating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ? max ? cycle time limit is ? dc ? (no clock) for all devices. 3: instruction cycle period (t cy ) equals four times the input oscillator time base period.
pic16c5x pic16c54/55/56/57 ds30453c-page 70 preliminary ? 2000 microchip technology inc. figure 10-3: clkout and i/o timing - pic16c54/55/56/57 table 10-2: clkout and i/o timing requirements - pic16c54/55/56/57 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 10.1, section 10.2 and section 10.3 parameter no. sym characteristic min typ (1) max units 10 tosh2ckl osc1 to clkout (2) ? 15 30** ns 11 tosh2ckh osc1 to clkout (2) ? 15 30** ns 12 tckr clkout rise time (2) ? 515**ns 13 tckf clkout fall time (2) ? 515**ns 14 tckl2iov clkout to port out valid (2) ?? 40** ns 15 tiov2ckh port in valid before clkout (2) 0.25 tcy+30* ?? ns 16 tckh2ioi port in hold after clkout (2) 0* ?? ns 17 tosh2iov osc1 (q1 cycle) to port out valid (3) ?? 100* ns 18 tosh2ioi osc1 (q2 cycle) to port input invalid (i/o in hold time) tbd ?? ns 19 tiov2osh port input valid to osc1 (i/o in setup time) tbd ?? ns 20 tior port output rise time (3) ? 10 25** ns 21 tiof port output fall time (3) ? 10 25** ns * these parameters are characterized but not tested. ** these parameters are design targets and are not tested. no characterization data available at this time. note 1: data in the typical ( ? typ ? ) column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: measurements are taken in rc mode where clkout output is 4 x t osc . 3: see figure 10-1 for loading conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 18 15 11 12 16 old value new value note: all tests must be done with specified capacitive loads (see data sheet) 50 pf on i/o pins and clkout. 19
? 2000 microchip technology inc. preliminary ds30453c-page 71 pic16c54/55/56/57 pic16c5x figure 10-4: reset, watchdog timer, and device reset timer timing - pic16c54/55/56/57 table 10-3: reset, watchdog timer, and device reset timer - pic16c54/55/56/57 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 10.1, section 10.2 and section 10.3 parameter no. sym characteristic min typ (1) max units conditions 30 tmcl mclr pulse width (low) 100* ?? ns v dd = 5.0v 31 twdt watchdog timer time-out period (no prescaler) 9* 18* 30* ms v dd = 5.0v (commercial) 32 t drt device reset timer period 9* 18* 30* ms v dd = 5.0v (commercial) 34 tio z i/o hi-impedance from mclr low ?? 100* ns * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por drt time-out internal reset watchdog timer reset 32 31 34 i/o pin 32 32 34 (note 1) note 1: i/o pins must be taken out of hi-impedance mode by enabling the output drivers in software. 30
pic16c5x pic16c54/55/56/57 ds30453c-page 72 preliminary ? 2000 microchip technology inc. figure 10-5: timer0 clock timings - pic16c54/55/56/57 table 10-4: timer0 clock requirements - pic16c54/55/56/57 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 10.1, section 10.2 and section 10.3 parameter no. sym characteristic min typ (1) max units conditions 40 tt0h t0cki high pulse width- no prescaler 0.5 t cy + 20* ?? ns - with prescaler 10* ?? ns 41 tt0l t0cki low pulse width- no prescaler 0.5 t cy + 20* ?? ns - with prescaler 10* ?? ns 42 tt0p t0cki period 20 or t cy + 40 * n ?? ns whichever is greater. n = prescale value (1, 2, 4,..., 256) * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. t0cki 40 41 42
? 2000 microchip technology inc. preliminary ds30453c-page 73 pic16c54/55/56/57 pic16c5x 11.0 dc and ac characteristics - pic16c54/55/56/57 the graphs and tables provided in this section are for design guidance and are not tested. in some graphs or tables, the data presented is outside specified operating range (e.g., outside specified v dd range). this is for information only and devices will operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. ? typical ? represents the mean of the distribution while ? max ? or ? min ? represents (mean + 3 ) and (mean ? 3 ) respectively, where is standard deviation. figure 11-1: typical rc oscillator frequency vs. temperature table 11-1: rc oscillator frequencies c ext r ext average f osc @ 5 v, 25 c 20 pf 3.3 k 4.973 mhz 27% 5 k 3.82 mhz 21% 10 k 2.22 mhz 21% 100 k 262.15 khz 31% 100 pf 3.3 k 1.63 mhz 13% 5 k 1.19 mhz 13% 10 k 684.64 khz 18% 100 k 71.56 khz 25% 300 pf 3.3 k 660 khz 10% 5.0 k 484.1 khz 14% 10 k 267.63 khz 15% 160 k 29.44 khz 19% the frequencies are measured on dip packages. the percentage variation indicated here is part-to-part variation due to normal process distribution. the variation indicated is 3 standard deviations from the average value for v dd = 5 v. f osc f osc (25 c) 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 010 20253040506070 t( c) frequency normalized to +25 c v dd = 5.5 v v dd = 3.5 v r ext 10 k ? c ext = 100 pf 0.88
pic16c5x pic16c54/55/56/57 ds30453c-page 74 preliminary ? 2000 microchip technology inc. figure 11-2: typical rc oscillator frequency vs. v dd , c ext = 20 p f 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) f osc (mhz) r = 3.3k r = 5k r = 10k r = 100k measured on dip packages, t = 25 c figure 11-3: typical rc oscillator frequency vs. v dd , c ext = 100 p f figure 11-4: typical rc oscillator frequency vs. v dd , c ext = 300 p f 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) f osc (mhz) r = 3.3k r = 5k r = 10k r = 100k measured on dip packages, t = 25 c 800 700 600 500 400 300 200 100 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) f osc (khz) r = 3.3k r = 5k r = 10k r = 100k measured on dip packages, t = 25 c
? 2000 microchip technology inc. preliminary ds30453c-page 75 pic16c54/55/56/57 pic16c5x figure 11-5: typical i pd vs. v dd , watchdog disabled figure 11-6: maximum i pd vs. v dd , watchdog disabled 2.5 2.0 1.5 1.0 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( a) v dd (volts) t = 25 c 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd (a) v dd (volts) 1 6.5 7.0 10 100 +85 c 0 c ? 40 c ? 55 c +125 c +70 c figure 11-7: typical i pd vs. v dd , watchdog enabled figure 11-8: maximum i pd vs. v dd , watchdog enabled 20 16 12 8 4 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( a) v dd (volts) 2 6 10 14 18 t = 25 c +70 c 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( a) v dd (volts) 6.5 7.0 40 60 +85 c ? 40 c ? 55 c 10 20 30 50 +125 c 0 c i pd , with wdt enabled, has two components: the leakage current, which increases with higher tempera- ture, and the operating current of the wdt logic, which increases with lower temperature. at ? 40 c, the latter domi- nates explaining the apparently anomalous behavior.
pic16c5x pic16c54/55/56/57 ds30453c-page 76 preliminary ? 2000 microchip technology inc. figure 11-9: v th (input threshold voltage) of i/o pins vs. v dd figure 11-10: v ih , v il of mclr , t0cki and osc1 (in rc mode) vs. v dd figure 11-11: v th (input threshold voltage) of osc1 input (in xt, hs, and lp modes) vs. v dd 2.00 1.80 1.60 1.40 1.20 1.00 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) m i n ( ? 4 0 c t o + 8 5 c ) 0.80 0.60 5.5 6.0 m a x ( ? 4 0 c t o + 8 5 c ) t y p ( + 2 5 c ) v th (volts) 3.5 3.0 2.5 2.0 1.5 1.0 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 0.5 0.0 5.5 6.0 v ih , v il (volts) 4.0 4.5 v i h m i n ( ? 4 0 c t o + 8 5 c ) v i h m a x ( ? 4 0 c t o + 8 5 c ) v i h t y p + 2 5 c v i l m i n ( ? 4 0 c t o + 8 5 c ) v i l m a x ( ? 4 0 c t o + 8 5 c ) v i h t y p + 2 5 c note: these input pins have schmitt trigger input buffers. 2.4 2.2 2.0 1.8 1.6 1.4 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 1.2 1.0 5.5 6.0 t y p ( + 2 5 c ) v th (volts) 2.6 2.8 3.0 3.2 3.4 m a x ( ? 4 0 c t o + 8 5 c ) m i n ( ? 4 0 c t o + 8 5 c )
? 2000 microchip technology inc. preliminary ds30453c-page 77 pic16c54/55/56/57 pic16c5x figure 11-12: typical i dd vs. frequency (external clock, 25 c) figure 11-13: maximum i dd vs. frequency (external clock, ? 40 c to +85 c) 10k 100k 1m 10m 100m 0.01 0.1 1.0 10 i dd (ma) external clock frequency (hz) 5.0 4.5 4.0 2.5 3.0 3.5 5.5 6.0 6.5 7.0 10k 100k 1m 10m 100m 0.01 0.1 1.0 10 i dd (ma) external clock frequency (hz) 5.0 4.5 4.0 3.5 5.5 6.0 6.5 7.0 2.5 3.0
pic16c5x pic16c54/55/56/57 ds30453c-page 78 preliminary ? 2000 microchip technology inc. figure 11-14: maximum i dd vs. frequency (external clock ? 55 c to +125 c) 10k 100k 1m 10m 100m 0.01 0.1 1.0 10 i dd (ma) external clock frequency (hz) 5.0 4.5 4.0 2.5 3.0 3.5 5.5 6.0 6.5 7.0 figure 11-15: wdt timer time-out period vs. v dd figure 11-16: transconductance (gm) of hs oscillator vs. v dd 50 45 40 35 30 25 20 15 10 5 234567 v dd (volts) wdt period (ms) max +85 c max +70 c typ +25 c min 0 c min ? 40 c 9000 8000 7000 6000 5000 4000 3000 2000 100 0 234567 v dd (volts) gm ( a/v) min +85 c max ? 40 c typ +25 c
? 2000 microchip technology inc. preliminary ds30453c-page 79 pic16c54/55/56/57 pic16c5x figure 11-17: transconductance (gm) of lp oscillator vs. v dd figure 11-18: i oh vs. v oh , v dd = 3 v 45 40 35 30 25 20 15 10 5 0 234567 v dd (volts) gm ( a/v) min +85 c max ? 40 c typ +25 c 0 ? 5 ? 10 ? 15 ? 20 ? 25 0 0.5 1.0 1.5 2.0 2.5 v oh (volts) i oh (ma) min +85 c 3.0 typ +25 c max ? 40 c figure 11-19: transconductance (gm) of xt oscillator vs. v dd figure 11-20: i oh vs. v oh , v dd = 5 v 2500 2000 1500 1000 500 0 234567 v dd (volts) gm ( a/v) min +85 c max ? 40 c typ +25 c 0 ? 10 ? 20 ? 30 ? 40 1.5 2.0 2.5 3.0 3.5 4.0 v oh (volts) i oh (ma) min +85 c max ? 40 c 4.5 5.0 typ +25 c
pic16c5x pic16c54/55/56/57 ds30453c-page 80 preliminary ? 2000 microchip technology inc. figure 11-21: i ol vs. v ol , v dd = 3 v table 11-2: input capacitance for pic16c54/56 pin typical capacitance (pf) 18l pdip 18l soic ra port 5.0 4.3 rb port 5.0 4.3 mclr 17.0 17.0 osc1 4.0 3.5 osc2/clkout 4.3 3.5 t0cki 3.2 2.8 all capacitance values are typical at 25 c. a part-to-part variation of 25% (three standard deviations) should be taken into account. 45 40 35 30 25 20 15 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 v ol (volts) i ol (ma) min +85 c max ? 40 c typ +25 c 3.0 figure 11-22: i ol vs. v ol , v dd = 5 v table 11-3: input capacitance for pic16c55/57 pin typical capacitance (pf) 28l pdip (600 mil) 28l soic ra port 5.2 4.8 rb port 5.6 4.7 rc port 5.0 4.1 mclr 17.0 17.0 osc1 6.6 3.5 osc2/clkout 4.6 3.5 t0cki 4.5 3.5 all capacitance values are typical at 25 c. a part-to-part variation of 25% (three standard deviations) should be taken into account. 90 80 70 60 50 40 30 20 10 0 0.00.51.01.52.02.5 v ol (volts) i ol (ma) min +85 c max ? 40 c typ +25 c 3.0
? 2000 microchip technology inc. preliminary ds30453c-page 81 pic16cr54a pic16c5x 12.0 electrical characteristics - pic16cr54a absolute maximum ratings ? ambient temperature under bias ................................................................................................. .......... ? 55 c to +125 c storage temperature ............................................................................................................ ................. ? 65 c to +150 c voltage on v dd with respect to v ss ..................................................................................................................0 to +7.5v voltage on mclr with respect to v ss (2) ............................................................................................................0 to +14v voltage on all other pins with respect to v ss ................................................................................. ? 0.6v to (v dd + 0.6v) total power dissipation (1) ............................................................................................................................... .....800 mw max. current out of v ss pin ........................................................................................................................... .......150 ma max. current into v dd pin ........................................................................................................................... ............50 ma max. current into an input pin (t0cki only) .................................................................................................................... 500 a input clamp current, i ik (vi < 0 or vi > v dd ) ................................................................................................................... 20 ma output clamp current, i ok (v0 < 0 or v0 > v dd ) ............................................................................................................. 20 ma max. output current sunk by any i/o pin........................................................................................ ........................25 ma max. output current sourced by any i/o pin..................................................................................... ......................20 ma max. output current sourced by a single i/o port (porta or b) .................................................................. .........40 ma max. output current sunk by a single i/o port (porta or b)..................................................................... ............50 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd - i oh } + {(v dd -v oh ) x i oh } + (v ol x i ol ) 2: voltage spikes below vss at the mclr pin, inducing currents greater than 80 ma may cause latch-up. thus, a series resistor of 50 to 100 ? should be used when applying a low level to the mclr pin rather than pulling this pin directly to vss. ? notice: stresses above those listed under "maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indi- cated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16c5x pic16cr54a ds30453c-page 82 preliminary ? 2000 microchip technology inc. 12.1 dc characteristics: pic16cr54a-04, 10, 20 (commercial ) pic16cr54a-04i, 10i, 20i (industrial) dc characteristics power supply pins standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) characteristic sym min typ (1) max units conditions supply voltage rc and xt options hs option v dd 2.5 4.5 6.25 5.5 v v ram data retention voltage (2) v dr ? 1.5* ? v device in sleep mode v dd start voltage to ensure power-on reset v por ? v ss ? v see section 7.4 for details on power-on reset v dd rise rate to ensure power-on reset s vdd 0.05* ?? v/ms see section 7.4 for details on power-on reset supply current (3) rc (4) and xt options hs option i dd 2.0 0.8 90 4.8 9.0 3.6 1.8 350 10 20 ma ma a ma ma f osc = 4.0 mhz, v dd = 6.0v f osc = 4.0 mhz, v dd = 3.0v f osc = 200 khz, v dd = 2.5v f osc = 10 mhz, v dd = 5.5v f osc = 20 mhz, v dd = 5.5v power-down current (5) commercial i pd 1.0 2.0 3.0 5.0 6.0 8.0* 15 25 a a a a v dd = 2.5v, wdt disabled v dd = 4.0v, wdt disabled v dd = 6.0v, wdt disabled v dd = 6.0v, wdt enabled power-down current (5) industrial i pd 1.0 2.0 3.0 3.0 5.0 8.0 10* 20* 18 45 a a a a a v dd = 2.5v, wdt disabled v dd = 4.0v, wdt disabled v dd = 4.0v, wdt enabled v dd = 6.0v, wdt disabled v dd = 6.0v, wdt enabled * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? . 5: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss .
? 2000 microchip technology inc. preliminary ds30453c-page 83 pic16cr54a pic16c5x 12.2 dc characteristics: pic16cr54a-04e, 10e, 20e (extended ) dc characteristics power supply pins standard operating conditions (unless otherwise specified) operating temperature ? 40 c t a +125 c (extended) characteristic sym min typ (1) max units conditions supply voltage rc, xt and lp options hs options v dd 3.25 4.5 ? ? 6.0 5.5 v v ram data retention voltage (2) v dr ? 1.5* ? v device in sleep mode v dd start voltage to ensure power-on reset v por ? v ss ? v see section 7.4 for details on power-on reset v dd rise rate to ensure power-on reset s vdd 0.05* ?? v/ms see section 7.4 for details on power-on reset supply current (3) rc (4) and xt options hs option i dd ? ? ? 1.8 4.8 9.0 3.3 10 20 ma ma ma f osc = 4.0 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 16 mhz, v dd = 5.5v power-down current (5) i pd ? ? 5.0 0.8 22 18 a a v dd = 3.25v, wdt enabled v dd = 3.25v, wdt disabled * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? . 5: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss .
pic16c5x pic16cr54a ds30453c-page 84 preliminary ? 2000 microchip technology inc. 12.3 dc characteristics: pic16lcr54a-04 (commercial ) pic16lcr54a-04i (industrial) dc characteristics power supply pins standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) characteristic sym min typ (1) max units conditions supply voltage v dd 2.0 ? 6.25 v lp option ram data retention voltage (2) v dr ? 1.5* ? v device in sleep mode v dd start voltage to ensure power-on reset v por ? v ss ? v see section 7.4 for details on power-on reset v dd rise rate to ensure power-on reset s vdd 0.05* ?? v/ms see section 7.4 for details on power-on reset supply current (3) i dd ? 10 20 70 a a f osc = 32 khz, v dd = 2.0v f osc = 32 khz, v dd = 6.0v power-down current (5) commercial i pd ? ? ? ? 1.0 2.0 3.0 5.0 6.0 8.0* 15 25 a a a a v dd = 2.5v, wdt disabled v dd = 4.0v, wdt disabled v dd = 6.0v, wdt disabled v dd = 6.0v, wdt enabled power-down current (5) industrial i pd ? ? ? ? ? 1.0 2.0 3.0 3.0 5.0 8.0 10* 20* 18 45 a a a a a v dd = 2.5v, wdt disabled v dd = 4.0v, wdt disabled v dd = 4.0v, wdt enabled v dd = 6.0v, wdt disabled v dd = 6.0v, wdt enabled * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? . 5: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss .
? 2000 microchip technology inc. preliminary ds30453c-page 85 pic16cr54a pic16c5x 12.4 dc characteristics: pic16cr54a-04, 10, 20, pic16lcr54a-04 (commercial) pic16cr54a-04i, 10i, 20i, pic16lcr54a-04i (industrial) dc characteristics all pins except power supply pins standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) operating voltage v dd range is described in section 12.1 and section 12.3. characteristic sym min typ (1) max units conditions input low voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) osc1 v il v ss v ss v ss v ss v ss ? ? ? ? ? 0.2 v dd 0.15 v dd 0.15 v dd 0.15 v dd 0.15 v dd v v v v v pin at hi-impedance rc option only (4) xt, hs and lp options input high voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) osc1 v ih 2.0 0.6 v dd 0.85 v dd 0.85 v dd 0.85 v dd 0.85 v dd ? ? ? ? ? ? v dd v dd v dd v dd v dd v dd v v v v v v v dd = 3.0v to 5.5v (5) full v dd range (5) rc option only (4) xt, hs and lp options hysteresis of schmitt trigger inputs v hys 0.15v dd * ?? v input leakage current (3) i/o ports mclr t0cki osc1 i il ? 1.0 ? 5.0 ? 3.0 ? 3.0 0.5 0.5 0.5 +1.0 +5.0 +3.0 +3.0 a a a a a for v dd 5.5v v ss v pin v dd , pin at hi-impedance v pin = v ss + 0.25v (2) v pin = v dd (2) v ss v pin v dd v ss v pin v dd , xt, hs and lp options output low voltage i/o ports osc2/clkout v ol ? ? ? ? 0.5 0.5 v v i ol = 10 ma, v dd = 6.0v i ol = 1.9 ma, v dd = 6.0v, rc option only output high voltage (3) i/o ports osc2/clkout v oh v dd ? 0.5 v dd ? 0.5 ? ? ? ? v v i oh = ? 4.0 ma, v dd = 6.0v i oh = ? 0.8 ma, v dd = 6.0v, rc option only * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltage. 3: negative current is defined as coming out of the pin. 4: for the rc option, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c5x be driven with external clock in rc mode. 5: the user may use the better of the two specifications.
pic16c5x pic16cr54a ds30453c-page 86 preliminary ? 2000 microchip technology inc. 12.5 dc characteristics: pic16cr54a-04e, 10e, 20e (extended) dc characteristics all pins except power supply pins standard operating conditions (unless otherwise specified) operating temperature ? 40 c t a +125 c operating voltage v dd range is described in section 12.2. characteristic sym min typ (1) max units conditions input low voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) osc1 v il vss vss vss vss vss ? ? ? ? ? 0.15 v dd 0.15 v dd 0.15 v dd 0.15 v dd 0.3 v dd v v v v v pin at hi-impedance rc option only (4) xt, hs and lp options input high voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) osc1 v ih 0.45 v dd 2.0 0.36 v dd 0.85 v dd 0.85 v dd 0.85 v dd 0.7 v dd ? ? ? ? ? ? ? v dd v dd v dd v dd v dd v dd v dd v v v v v v v for all v dd (5) 4.0v < v dd 5.5v (5) v dd > 5.5v rc option only (4) xt, hs and lp options hysteresis of schmitt trigger inputs v hys 0.15v dd * ?? v input leakage current (3) i/o ports mclr t0cki osc1 i il ? 1.0 ? 5.0 ? 3.0 ? 3.0 0.5 0.5 0.5 0.5 +1.0 +5.0 +3.0 +3.0 a a a a a for v dd 5.5v v ss v pin v dd , pin at hi-impedance v pin = v ss + 0.25v (2) v pin = v dd (2) v ss v pin v dd v ss v pin v dd , xt, hs and lp options output low voltage i/o ports osc2/clkout v ol ? ? ? ? 0.6 0.6 v v i ol = 8.7 ma, v dd = 4.5v i ol = 1.6 ma, v dd = 4.5v, rc option only output high voltage (3) i/o ports osc2/clkout v oh v dd ? 0.7 v dd ? 0.7 ? ? ? ? v v i oh = ? 5.4 ma, v dd = 4.5v i oh = ? 1.0 ma, v dd = 4.5v, rc option only * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltage. 3: negative current is defined as coming out of the pin. 4: for the rc option, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c5x be driven with external clock in rc mode. 5: the user may use the better of the two specifications.
? 2000 microchip technology inc. preliminary ds30453c-page 87 pic16cr54a pic16c5x 12.6 timing parameter symbology and load conditions the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 2. tpps t f frequency t time lowercase subscripts (pp) and their meanings: pp 2to mcmclr ck clkout osc oscillator cy cycle time os osc1 drt device reset timer t0 t0cki io i/o port wdt watchdog timer uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance figure 12-1: load conditions c l v ss pin c l = 50 pf for all pins except osc2 15 pf for osc2 in xt, hs or lp options when external clock is used to drive osc1
pic16c5x pic16cr54a ds30453c-page 88 preliminary ? 2000 microchip technology inc. 12.7 timing diagrams and specifications figure 12-2: external clock timing - pic16cr54a table 12-1: external clock timing requirements - pic16cr54a ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 12.1, section 12.2 and section 12.3. parameter no. sym characteristic min typ (1) max units conditions f osc external clkin frequency (2) dc ? 4.0 mhz xt osc mode dc ? 4.0 mhz hs osc mode (04) dc ? 10 mhz hs osc mode (10) dc ? 20 mhz hs osc mode (20) dc ? 200 khz lp osc mode oscillator frequency (2) dc ? 4.0 mhz rc osc mode 0.1 ? 4.0 mhz xt osc mode 4.0 ? 4.0 mhz hs osc mode (04) 4.0 ? 10 mhz hs osc mode (10) 4.0 ? 20 mhz hs osc mode (20) 5.0 ? 200 khz lp osc mode * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: all specified values are based on characterization data for that particular oscillator type under standard oper- ating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ? max ? cycle time limit is ? dc ? (no clock) for all devices. 3: instruction cycle period (t cy ) equals four times the input oscillator time base period. osc1 clkout q4 q1 q2 q3 q4 q1 133 44 2
? 2000 microchip technology inc. preliminary ds30453c-page 89 pic16cr54a pic16c5x 1t osc external clkin period (2) 250 ?? ns xt osc mode 250 ?? ns hs osc mode (04) 100 ?? ns hs osc mode (10) 50 ?? ns hs osc mode (20) 5.0 ?? slp osc mode oscillator period (2) 250 ?? ns rc osc mode 250 ? 10,00 0 ns xt osc mode 250 ? 250 ns hs osc mode (04) 100 ? 250 ns hs osc mode (10) 50 ? 250 ns hs osc mode (20) 5.0 ? 200 slp osc mode 2t cy instruction cycle time (3) ? 4/f os c ?? 3 tosl, tosh clock in (osc1) low or high time 50* ?? ns xt oscillator 20* ?? ns hs oscillator 2.0* ?? s lp oscillator 4 tosr, tosf clock in (osc1) rise or fall time ?? 25* ns xt oscillator ?? 25* ns hs oscillator ?? 50* ns lp oscillator table 12-1: external clock timing requirements - pic16cr54a (con ? t) ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 12.1, section 12.2 and section 12.3. parameter no. sym characteristic min typ (1) max units conditions * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: all specified values are based on characterization data for that particular oscillator type under standard oper- ating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ? max ? cycle time limit is ? dc ? (no clock) for all devices. 3: instruction cycle period (t cy ) equals four times the input oscillator time base period.
pic16c5x pic16cr54a ds30453c-page 90 preliminary ? 2000 microchip technology inc. figure 12-3: clkout and i/o timing - pic16cr54a table 12-2: clkout and i/o timing requirements - pic16cr54a ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 12.1, section 12.2 and section 12.3. parameter no. sym characteristic min typ (1) max units 10 tosh2ckl osc1 to clkout (2) ? 15 30** ns 11 tosh2ckh osc1 to clkout (2) ? 15 30** ns 12 tckr clkout rise time (2) ? 5.0 15** ns 13 tckf clkout fall time (2) ? 5.0 15** ns 14 tckl2iov clkout to port out valid (2) ?? 40** ns 15 tiov2ckh port in valid before clkout (2) 0.25 tcy+30* ?? ns 16 tckh2ioi port in hold after clkout (2) 0* ?? ns 17 tosh2iov osc1 (q1 cycle) to port out valid (3) ?? 100* ns 18 tosh2ioi osc1 (q2 cycle) to port input invalid (i/o in hold time) tbd ?? ns 19 tiov2osh port input valid to osc1 (i/o in setup time) tbd ?? ns 20 tior port output rise time (3) ? 10 25** ns 21 tiof port output fall time (3) ? 10 25** ns * these parameters are characterized but not tested. ** these parameters are design targets and are not tested. no characterization data available at this time. note 1: data in the typical ( ? typ ? ) column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: measurements are taken in rc mode where clkout output is 4 x t osc . 3: see figure 12-1 for loading conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 14 17 20, 21 18 15 11 16 old value new value note: all tests must be done with specified capacitive loads (see data sheet) 50 pf on i/o pins and clkout. 19 12 13
? 2000 microchip technology inc. preliminary ds30453c-page 91 pic16cr54a pic16c5x figure 12-4: reset, watchdog timer, and device reset timer timing - pic16cr54a table 12-3: reset, watchdog timer, and device reset timer - pic16cr54a ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 12.1, section 12.2 and section 12.3. parameter no. sym characteristic min typ (1) max units conditions 30 tmcl mclr pulse width (low) 1.0* ?? sv dd = 5.0v 31 twdt watchdog timer time-out period (no prescaler) 7.0* 18* 40* ms v dd = 5.0v (commercial) 32 t drt device reset timer period 7.0* 18* 30* ms v dd = 5.0v (commercial) 34 tio z i/o hi-impedance from mclr low ?? 1.0* s * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por drt time-out internal reset watchdog timer reset 32 31 34 i/o pin 32 32 34 (note 1) note 1: i/o pins must be taken out of hi-impedance mode by enabling the output drivers in software. 30
pic16c5x pic16cr54a ds30453c-page 92 preliminary ? 2000 microchip technology inc. figure 12-5: timer0 clock timings - pic16cr54a table 12-4: timer0 clock requirements - pic16cr54a ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 12.1, section 12.2 and section 12.3. param no. sym characteristic min typ (1) max units conditions 40 tt0h t0cki high pulse width - no prescaler 0.5 t cy + 20* ?? ns - with prescaler 10* ?? ns 41 tt0l t0cki low pulse width - no prescaler 0.5 t cy + 20* ?? ns - with prescaler 10* ?? ns 42 tt0p t0cki period 20 or t cy + 40 * n ?? ns whichever is greater. n = prescale value (1, 2, 4,..., 256) * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. t0cki 40 41 42
? 2000 microchip technology inc. preliminary ds30453c-page 93 pic16c54a pic16c5x 13.0 electrical characteristics - pic16c54a absolute maximum ratings ? ambient temperature under bias................................................................................................. ........... ? 55 c to +125 c storage temperature ............................................................................................................ ................. ? 65 c to +150 c voltage on v dd with respect to v ss ..................................................................................................................0 to +7.5v voltage on mclr with respect to v ss ...............................................................................................................0 to +14v voltage on all other pins with respect to v ss ................................................................................. ? 0.6v to (v dd + 0.6v) total power dissipation (1) ............................................................................................................................... ......800 mw max. current out of v ss pin ........................................................................................................................... ........150 ma max. current into v dd pin ........................................................................................................................... ...........100 ma max. current into an input pin (t0cki only) ..................................................................................................................... 500 a input clamp current, i ik (v i < 0 or v i > v dd ) .................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) .............................................................................................................. 20 ma max. output current sunk by any i/o pin ........................................................................................ .........................25 ma max. output current sourced by any i/o pin ..................................................................................... .......................20 ma max. output current sourced by a single i/o port (porta or b) .................................................................. ...........50 ma max. output current sunk by a single i/o port (porta or b) ..................................................................... .............50 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - i oh } + {(v dd -v oh ) x i oh } + (v ol x i ol ) ? notice: stresses above those listed under "maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indi- cated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16c5x pic16c54a ds30453c-page 94 preliminary ? 2000 microchip technology inc. 13.1 dc characteristics: pic16c54a-04, 10, 20 (commercial) pic16c54a-04i, 10i, 20i (industrial) dc characteristics power supply pins standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) characteristic sym min typ (1) max units conditions supply voltage xt, rc and lp options hs option v dd 3.0 4.5 ? ? 6.25 5.5 v v ram data retention voltage (2) v dr ? 1.5* ? v device in sleep mode v dd start voltage to ensure power-on reset v por ? v ss ? v see section 7.4 for details on power-on reset v dd rise rate to ensure power-on reset s vdd 0.05* ?? v/ms see section 7.4 for details on power-on reset supply current (3) xt and rc (4) options hs option lp option, commercial lp option, industrial i dd ? ? ? ? ? 1.8 2.4 4.5 14 17 2.4 8.0 16 29 37 ma ma ma a a f osc = 4.0 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 20 mhz, v dd = 5.5v f osc = 32 khz, v dd = 3.0v, wdt disabled f osc = 32 khz, v dd = 3.0v, wdt disabled power-down current (5) commercial industrial i pd ? ? ? ? 4.0 0.25 5.0 0.3 12 4.0 14 5.0 a a a a v dd = 3.0v, wdt enabled v dd = 3.0v, wdt disabled v dd = 3.0v, wdt enabled v dd = 3.0v, wdt disabled * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? . 5: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss .
? 2000 microchip technology inc. preliminary ds30453c-page 95 pic16c54a pic16c5x 13.2 dc characteristics: pic16c54a-04e, 10e, 20e (extended) dc characteristics power supply pins standard operating conditions (unless otherwise specified) operating temperature ? 40 c t a +125 c (extended) characteristic sym min typ (1) max units conditions supply voltage xt and rc options hs option v dd 3.5 4.5 ? ? 5.5 5.5 v v ram data retention voltage (2) v dr ? 1.5* ? v device in sleep mode v dd start voltage to ensure power-on reset v por ? v ss ? v see section 7.4 for details on power-on reset v dd rise rate to ensure power-on reset s vdd 0.05* ?? v/ms see section 7.4 for details on power-on reset supply current (3) xt and rc (4) options hs option i dd ? ? ? 1.8 4.8 9.0 3.3 10 20 ma ma ma f osc = 4.0 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 20 mhz, v dd = 5.5v power-down current (5) xt and rc options hs option i pd ? ? ? ? 5.0 0.8 4.0 0.25 22 18 22 18 a a a a v dd = 3.5v, wdt enabled v dd = 3.5v, wdt disabled v dd = 3.5v, wdt enabled v dd = 3.5v, wdt disabled * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? . 5: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss .
pic16c5x pic16c54a ds30453c-page 96 preliminary ? 2000 microchip technology inc. 13.3 dc characteristics: pic16lc54a-04 (commercial) pic16lc54a-04i (industrial)) dc characteristics power supply pins standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) characteristic sym min typ (1) max units conditions supply voltage xt and rc options lp options v dd 3.0 2.5 ? ? 6.25 6.25 v v ram data retention voltage (2) v dr ? 1.5* ? v device in sleep mode v dd start voltage to ensure power-on reset v por ? v ss ? v see section 7.4 for details on power-on reset v dd rise rate to ensure power-on reset s vdd 0.05* ?? v/ms see section 7.4 for details on power-on reset supply current (3) xt and rc (4) options lp option, commercial lp option, industrial lp option, extended i dd ? ? ? ? 0.5 11 11 11 2.5 27 35 37 ma a a a f osc = 4.0 mhz, v dd = 5.5v f osc = 32 khz, v dd = 2.5v wdt disabled f osc = 32 khz, v dd = 2.5v wdt disabled f osc = 32 khz, v dd = 2.5v wdt disabled power-down current (5) commercial industrial extended i pd ? ? ? ? ? ? 2.5 0.25 2.5 0.25 2.5 0.25 12 4.0 14 5.0 15 7.0 a a a a a a v dd = 2.5v, wdt enabled v dd = 2.5v, wdt disabled v dd = 2.5v, wdt enabled v dd = 2.5v, wdt disabled v dd = 2.5v, wdt enabled v dd = 2.5v, wdt disabled * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? . 5: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss .
? 2000 microchip technology inc. preliminary ds30453c-page 97 pic16c54a pic16c5x 13.4 dc characteristics: pic16c54a-04, 10, 20, pic16lc54a-04, pic16lv54a-02 (commercial) pic16c54a-04i, 10i, 20i, pic16lc54a-04i, pic16lv54a-02i (industrial) pic16c54a-04e, 10e, 20e (extended) dc characteristics all pins except power supply pins standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 20 c t a +85 c (industrial - pic16lv54a-02i) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 13.1, section 13.2 and section 13.3. characteristic sym min typ (1) max units conditions input low voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) osc1 v il v ss v ss v ss v ss v ss ? ? ? ? ? 0.2 v dd 0.15 v dd 0.15 v dd 0.15 v dd 0.3 v dd v v v v pin at hi-impedance rc option only (4) xt, hs and lp options input high voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) osc1 v ih 0.2 v dd +1v 2.0 0.85 v dd 0.85 v dd 0.85 v dd 0.7 v dd ? ? ? ? ? ? v dd v dd v dd v dd v dd v dd v v v v v v for all v dd (5) 4.0v < v dd 5.5v (5) rc option only (4) xt, hs and lp options hysteresis of schmitt trigger inputs v hys 0.15v dd * ?? v input leakage current (3) i/o ports mclr t0cki osc1 i il -1.0 ? -5.0 -3.0 -3.0 0.5 ? ? 0.5 0.5 0.5 +1.0 ? +5.0 +3.0 +3.0 ? a ? a a a a for v dd 5.5v v ss v pin v dd, pin at hi-impedance v pin = v ss +0.25v (2) v pin = v dd (2) v ss v pin v dd v ss v pin v dd, xt, hs and lp options output low voltage i/o ports osc2/clkout v ol ? ? ? ? 0.6 0.6 v v i o l = 8.7 ma, v dd = 4.5v i o l = 1.6 ma, v dd = 4.5v, rc option only output high voltage i/o ports (3) osc2/clkout v oh v dd -0.7 v dd -0.7 ? ? ? ? v v i o h = -5.4 ma, v dd = 4.5v i o h = -1.0 ma, v dd = 4.5v, rc option only * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input volt- age. 3: negative current is defined as coming out of the pin. 4: for the rc option, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c5x be driven with external clock in rc mode. 5: the user may use the better of the two specifications.
pic16c5x pic16c54a ds30453c-page 98 preliminary ? 2000 microchip technology inc. 13.5 timing parameter symbology and load conditions the timing parameter symbols have been created following one of the following formats: figure 13-1: load conditions - pic16c54a 1. tpps2pps 2. tpps t f frequency t time lowercase subscripts (pp) and their meanings: pp 2to mcmclr ck clkout osc oscillator cy cycle time os osc1 drt device reset timer t0 t0cki io i/o port wdt watchdog timer uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance c l v ss pin c l = 50 pf for all pins except osc2 15 pf for osc2 in xt, hs or lp options when external clock is used to drive osc1
? 2000 microchip technology inc. preliminary ds30453c-page 99 pic16c54a pic16c5x 13.6 timing diagrams and specifications figure 13-2: external clock timing - pic16c54a table 13-1: external clock timing requirements - pic16c54a ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 20 c t a +85 c (industrial - pic16lv54a-02i) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 13.1, section 13.2 and section 13.3. parameter no. sym characteristic min typ (1) max units conditions f osc external clkin frequency (2) dc ? 4.0 mhz xt osc mode dc ? 2.0 mhz xt osc mode (pic16lv54a) dc ? 4.0 mhz hs osc mode (04) dc ? 10 mhz hs osc mode (10) dc ? 20 mhz hs osc mode (20) dc ? 200 khz lp osc mode oscillator frequency (2) dc ? 4.0 mhz rc osc mode dc ? 2.0 mhz rc osc mode (pic16lv54a) 0.1 ? 4.0 mhz xt osc mode 0.1 ? 2.0 mhz xt osc mode (pic16lv54a) 4 ? 4.0 mhz hs osc mode (04) 4 ? 10 mhz hs osc mode (10) 4 ? 20 mhz hs osc mode (20) 5 ? 200 khz lp osc mode * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: all specified values are based on characterization data for that particular oscillator type under standard oper- ating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ? max ? cycle time limit is ? dc ? (no clock) for all devices. 3: instruction cycle period (t cy ) equals four times the input oscillator time base period. osc1 clkout q4 q1 q2 q3 q4 q1 133 44 2
pic16c5x pic16c54a ds30453c-page 100 preliminary ? 2000 microchip technology inc. 1t osc external clkin period (2) 250 ?? ns xt osc mode 500 ?? ns xt osc mode (pic16lv54a) 250 ?? ns hs osc mode (04) 100 ?? ns hs osc mode (10) 50 ?? ns hs osc mode (20) 5.0 ?? s lp osc mode oscillator period (2) 250 ?? ns rc osc mode 500 ?? ns rc osc mode (pic16lv54a) 250 ? 10,00 0 ns xt osc mode 500 ?? ns xt osc mode (pic16lv54a) 250 ? 250 ns hs osc mode (04) 100 ? 250 ns hs osc mode (10) 50 ? 250 ns hs osc mode (20) 5.0 ? 200 s lp osc mode 2t cy instruction cycle time (3) ? 4/f os c ?? 3 tosl, tosh clock in (osc1) low or high time 85* ?? ns xt oscillator 20* ?? ns hs oscillator 2.0* ?? s lp oscillator 4 tosr, tosf clock in (osc1) rise or fall time ?? 25* ns xt oscillator ?? 25* ns hs oscillator ?? 50* ns lp oscillator table 13-1: external clock timing requirements - pic16c54a (con ? t) ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 20 c t a +85 c (industrial - pic16lv54a-02i) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 13.1, section 13.2 and section 13.3. parameter no. sym characteristic min typ (1) max units conditions * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: all specified values are based on characterization data for that particular oscillator type under standard oper- ating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ? max ? cycle time limit is ? dc ? (no clock) for all devices. 3: instruction cycle period (t cy ) equals four times the input oscillator time base period.
? 2000 microchip technology inc. preliminary ds30453c-page 101 pic16c54a pic16c5x figure 13-3: clkout and i/o timing - pic16c54a table 13-2: clkout and i/o timing requirements - pic16c54a ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 20 c t a +85 c (industrial - pic16lv54a-02i) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 13.1, section 13.2 and section 13.3. parameter no. sym characteristic min typ (1) max units 10 tosh2ckl osc1 to clkout (2) ? 15 30** ns 11 tosh2ckh osc1 to clkout (2) ? 15 30** ns 12 tckr clkout rise time (2) ? 5.0 15** ns 13 tckf clkout fall time (2) ? 5.0 15** ns 14 tckl2iov clkout to port out valid (2) ?? 40** ns 15 tiov2ckh port in valid before clkout (2) 0.25 tcy+30* ?? ns 16 tckh2ioi port in hold after clkout (2) 0* ?? ns 17 tosh2iov osc1 (q1 cycle) to port out valid (3) ?? 100* ns 18 tosh2ioi osc1 (q2 cycle) to port input invalid (i/o in hold time) tbd ?? ns 19 tiov2osh port input valid to osc1 (i/o in setup time) tbd ?? ns 20 tior port output rise time (3) ? 10 25** ns 21 tiof port output fall time (3) ? 10 25** ns * these parameters are characterized but not tested. ** these parameters are design targets and are not tested. no characterization data available at this time. note 1: data in the typical ( ? typ ? ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: measurements are taken in rc mode where clkout output is 4 x t osc . 3: see figure 14-1 for loading conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 18 15 11 12 16 old value new value note: all tests must be done with specified capacitive loads (see data sheet) 50 pf on i/o pins and clkout. 19
pic16c5x pic16c54a ds30453c-page 102 preliminary ? 2000 microchip technology inc. figure 13-4: reset, watchdog timer, and device reset timer timing - pic16c54a table 13-3: reset, watchdog timer, and device reset timer - pic16c54a ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 20 c t a +85 c (industrial - pic16lv54a-02i) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 13.1, section 13.2 and section 13.3. parameter no. sym characteristic min typ (1) max units conditions 30 tmcl mclr pulse width (low) 100* 1s ? ? ? ? ns ? v dd = 5.0v v dd = 5.0v (pic16lv54a only) 31 twdt watchdog timer time-out period (no prescaler) 9.0* 18* 30* ms v dd = 5.0v (commercial) 32 t drt device reset timer period 9.0* 18* 30* ms v dd = 5.0v (commercial) 34 tio z i/o hi-impedance from mclr low ? ? ? ? 100* 1s ns ? (pic16lv54a only) * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por drt time-out internal reset watchdog timer reset 32 31 34 i/o pin 32 32 34 (note 1) note 1: i/o pins must be taken out of hi-impedance mode by enabling the output drivers in software. 30
? 2000 microchip technology inc. preliminary ds30453c-page 103 pic16c54a pic16c5x figure 13-5: timer0 clock timings - pic16c54a table 13-4: timer0 clock requirements - pic16c54a ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 20 c t a +85 c (industrial - pic16lv54a-02i) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 13.1, section 13.2 and section 13.3. param no. sym characteristic min typ (1) max units conditions 40 tt0h t0cki high pulse width - no prescaler 0.5 t cy + 20* ?? ns - with prescaler 10* ?? ns 41 tt0l t0cki low pulse width - no prescaler 0.5 t cy + 20* ?? ns - with prescaler 10* ?? ns 42 tt0p t0cki period 20 or t cy + 40 * n ?? ns whichever is greater. n = prescale value (1, 2, 4,..., 256) * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guid- ance only and are not tested. t0cki 40 41 42
pic16c5x pic16c54a ds30453c-page 104 preliminary ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. preliminary ds30453c-page 105 pic16c54a pic16c5x 14.0 dc and ac characteristics - pic16c54a the graphs and tables provided in this section are for design guidance and are not tested. in some graphs or tables, the data presented is outside specified operating range (e.g., outside specified v dd range). this is for information only and devices will operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. ? typical ? represents the mean of the distribution, while ? max ? or ? min ? represents (mean + 3 ) and (mean ? 3 ) respectively, where is standard deviation. figure 14-1: typical rc oscillator frequency vs. temperature table 14-1: rc oscillator frequencies c ext r ext average fosc @ 5 v, 25 c 20 pf 3.3 k 4.973 mhz 27% 5 k 3.82 mhz 21% 10 k 2.22 mhz 21% 100 k 262.15 khz 31% 100 pf 3.3 k 1.63 mhz 13% 5 k 1.19 mhz 13% 10 k 684.64 khz 18% 100 k 71.56 khz 25% 300 pf 3.3 k 660 khz 10% 5.0 k 484.1 khz 14% 10 k 267.63 khz 15% 160 k 29.44 khz 19% the frequencies are measured on dip packages. the percentage variation indicated here is part-to-part variation due to normal process distribution. the variation indicated is 3 standard deviation from average value for v dd = 5 v. f osc f osc (25 c) 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 010 20253040506070 t( c) frequency normalized to +25 c v dd = 5.5 v v dd = 3.5 v r ext 10 k ? c ext = 100 pf 0.88
pic16c5x pic16c54a ds30453c-page 106 preliminary ? 2000 microchip technology inc. figure 14-2: typical rc oscillator frequency vs. v dd , c ext = 20 p f figure 14-3: typical rc oscillator frequency vs. v dd , c ext = 100 p f 6.00 5.00 4.00 3.00 1.00 0.00 33.5 4 4.5 5 5.5 6 2.5 v dd (volts) 2.00 f osc (mhz) 2.00 c ext =20pf, t=25 c r=3.3k r=5.0k r=10k r=100k 6.00 5.00 4.00 3.00 1.00 0.00 33.5 4 4.5 5 5.5 6 2.5 v dd (volts) 2.00 6.00 5.00 4.00 3.00 1.00 0.00 33.5 4 4.5 5 5.5 6 2.5 v dd (volts) 2.00 f osc (mhz) c ext =100pf, t=25 c r=3.3k r=5.0k r=10k r=100k 1.80 1.60 1.00 0.40 0.00 33.5 4 4.5 5 5.5 6 2.5 v dd (volts) 0.60 1.20 0.80 0.20 1.40
? 2000 microchip technology inc. preliminary ds30453c-page 107 pic16c54a pic16c5x figure 14-4: typical rc oscillator frequency vs. v dd , c ext = 300 p f figure 14-5: typical i pd vs. v dd , watchdog disabled (25 c) f osc (khz) 700.00 600.00 500.00 400.00 300.00 200.00 100.00 0.00 2.5 3 3.5 4 4.5 5 5.5 6 c ext =300pf, t=25 c r=3.3k r=5.0k r=10k r=100k v dd (volts) 2.50 2.00 1.50 1.00 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 0.50 0 5.5 6.0 i pd ( a)
pic16c5x pic16c54a ds30453c-page 108 preliminary ? 2000 microchip technology inc. figure 14-6: v th (input threshold voltage) of i/o pins vs. v dd figure 14-7: v ih , v il of mclr , t0cki and osc1 (in rc mode) vs. v dd figure 14-8: v th (input threshold voltage) of osc1 input (in xt, hs, and lp modes) vs. v dd 2.00 1.80 1.60 1.40 1.20 1.00 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) m i n ( ? 4 0 c t o + 8 5 c ) 0.80 0.60 5.5 6.0 m a x ( ? 4 0 c t o + 8 5 c ) t y p ( + 2 5 c ) v th (volts) 3.5 3.0 2.5 2.0 1.5 1.0 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 0.5 0.0 5.5 6.0 v ih , v il (volts) 4.0 4.5 v i h m i n ( ? 4 0 c t o + 8 5 c ) v i h m a x ( ? 4 0 c t o + 8 5 c ) v i h t y p + 2 5 c v i l m i n ( ? 4 0 c t o + 8 5 c ) v i l m a x ( ? 4 0 c t o + 8 5 c ) v i h t y p + 2 5 c note: these input pins have schmitt trigger input buffers. 2.4 2.2 2.0 1.8 1.6 1.4 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 1.2 1.0 5.5 6.0 t y p ( + 2 5 c ) v th (volts) 2.6 2.8 3.0 3.2 3.4 m a x ( ? 4 0 c t o + 8 5 c ) m i n ( ? 4 0 c t o + 8 5 c )
? 2000 microchip technology inc. preliminary ds30453c-page 109 pic16c54a pic16c5x figure 14-9: typical i dd vs. frequency (wdt dis, rc mode @ 20 p f, 2 5 c) figure 14-10: maximum i dd vs. frequency (wdt dis, rc mode @ 20 p f, ? 40 c to +85 c) 10000 1000 100 10 0.1 1 10 i dd ( a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v freq (mhz) 10000 1000 100 10 1 10 i dd ( a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 0.1 freq (mhz)
pic16c5x pic16c54a ds30453c-page 110 preliminary ? 2000 microchip technology inc. figure 14-11: typical i dd vs. frequency (wdt dis, rc mode @ 100 p f, 2 5 c) figure 14-12: maximum i dd vs. frequency (wdt dis, rc mode @ 100 p f, ? 40 c to +85 c) 10000 1000 100 10 0.01 110 i dd ( a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v freq (mhz) 0.1 10000 1000 100 10 0.01 110 i dd ( a) freq (mhz) 0.1 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v
? 2000 microchip technology inc. preliminary ds30453c-page 111 pic16c54a pic16c5x figure 14-13: typical i dd vs. frequency (wdt dis, rc mode @ 300 p f, 2 5 c) figure 14-14: maximum i dd vs. frequency (wdt dis, rc mode @ 300 p f, ? 40 c to +85 c) 10000 1000 100 10 0.01 0.1 1 i dd ( a) freq (mhz) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 10000 1000 100 10 0.01 0.1 i dd ( a) 6.0v 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v freq (mhz) 1
pic16c5x pic16c54a ds30453c-page 112 preliminary ? 2000 microchip technology inc. figure 14-15: wdt timer time-out period vs. v dd table 14-2: input capacitance for pic16c54a/c58a 50 45 40 35 30 25 20 15 10 5 234567 v dd (volts) wdt period (ms) max +85 c max +70 c typ +25 c min 0 c min ? 40 c pin typical capacitance (pf) 18l pdip 18l soic ra port 5.0 4.3 rb port 5.0 4.3 mclr 17.0 17.0 osc1 4.0 3.5 osc2/clkout 4.3 3.5 t0cki 3.2 2.8 all capacitance values are typical at 25 c. a part-to-part variation of 25% (three standard deviations) should be taken into account.
? 2000 microchip technology inc. preliminary ds30453c-page 113 pic16c54a pic16c5x figure 14-16: transconductance (gm) of hs oscillator vs. v dd figure 14-17: transconductance (gm) of lp oscillator vs. v dd 9000 8000 7000 6000 5000 4000 3000 2000 100 0 234567 v dd (volts) gm ( a/v) min +85 c max ? 40 c typ +25 c 45 40 35 30 25 20 15 10 5 0 234567 v dd (volts) gm ( a/v) min +85 c max ? 40 c typ +25 c figure 14-18: transconductance (gm) of xt oscillator vs. v dd 2500 2000 1500 1000 500 0 234567 v dd (volts) gm ( a/v) min +85 c max ? 40 c typ +25 c
pic16c5x pic16c54a ds30453c-page 114 preliminary ? 2000 microchip technology inc. figure 14-19: i oh vs. v oh , v dd = 3 v figure 14-20: i oh vs. v oh , v dd = 5 v 0 ? 5 ? 10 ? 15 ? 20 ? 25 0 0.5 1.0 1.5 2.0 2.5 v oh (volts) i oh (ma) min +85 c 3.0 typ +25 c max ? 40 c 0 ? 10 ? 20 ? 30 ? 40 1.5 2.0 2.5 3.0 3.5 4.0 v oh (volts) i oh (ma) min +85 c max ? 40 c 4.5 5.0 typ +25 c figure 14-21: i ol vs. v ol , v dd = 3 v figure 14-22: i ol vs. v ol , v dd = 5 v 45 40 35 30 25 20 15 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 v ol (volts) i ol (ma) min +85 c max ? 40 c typ +25 c 3.0 90 80 70 60 50 40 30 20 10 0 0.00.51.01.52.02.5 v ol (volts) i ol (ma) min +85 c max ? 40 c typ +25 c 3.0
? 2000 microchip technology inc. preliminary ds30453c-page 115 pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/c58b/cr58b 15.0 electrical characteristics - pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/c58b/cr58b absolute maximum ratings ? ambient temperature under bias................................................................................................. ........... ? 55 c to +125 c storage temperature ............................................................................................................ ................. ? 65 c to +150 c voltage on v dd with respect to v ss ..................................................................................................................0 to +7.5v voltage on mclr with respect to v ss ...............................................................................................................0 to +14v voltage on all other pins with respect to v ss ................................................................................. ? 0.6v to (v dd + 0.6v) total power dissipation (1) ............................................................................................................................... ......800 mw max. current out of v ss pin ........................................................................................................................... ........150 ma max. current into v dd pin ........................................................................................................................... ...........100 ma max. current into an input pin (t0cki only) ..................................................................................................................... 500 a input clamp current, i ik (v i < 0 or v i > v dd ) .................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) .............................................................................................................. 20 ma max. output current sunk by any i/o pin ........................................................................................ .........................25 ma max. output current sourced by any i/o pin ..................................................................................... .......................20 ma max. output current sourced by a single i/o (port a, b or c) .................................................................. ...............50 ma max. output current sunk by a single i/o (port a, b or c) ...................................................................... .................50 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - i oh } + {(v dd -v oh ) x i oh } + (v ol x i ol ) ? notice: stresses above those listed under "maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indi- cated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16c5x ds30453c-page 116 preliminary ? 2000 microchip technology inc. figure 15-1: pic16c54c voltage-frequency graph, 0 c t a +70 c figure 15-2: pic16c54c voltage-frequency graph, -40 c t a < 0 c, +70 c < ta +125 c 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: the maximum rated speed of the part limits the permissible combinations of voltage and frequency. please reference the product identification system section for the maximum rated speed of the parts. 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 2.0 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: the maximum rated speed of the part limits the permissible combinations of voltage and frequency. please reference the product identification system section for the maximum rated speed of the parts.
? 2000 microchip technology inc. preliminary ds30453c-page 117 pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/c58b/cr58b 15.1 dc characteristics: pic16c54c/c55a/c56a/c57c/c58b-04, 20 (commercial) pic16 c r54c/cr56a/cr57c/cr58b-04, 20 (commercial) pic16c54c/c55a/c56a/c57c/c58b-04i, 20i (industrial) pic16cr54b/cr/54c/cr56a/cr57c/cr58b -04i, 20i (industrial) dc characteristics power supply pins standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) characteristic sym min typ (1) max units conditions supply voltage xt, rc, lp and hs options hs option v dd 3.0 4.5 ? ? 5.5 5.5 v v hs option from 0 - 10mhz hs option from 0 - 20mhz ram data retention voltage (2) v dr ? 1.5* ? v device in sleep mode v dd start voltage to ensure power-on reset v por ? v ss ? v see section 7.4 for details on power-on reset v dd rise rate to ensure power-on reset s vdd 0.05* ?? v/ms see section 7.4 for details on power-on reset supply current (3)(4) i dd ? ? ? ? ? 1.8 2.6 4.5 14 17 2.4 3.6 16 32 40 ma ma ma a a f osc = 4 mhz, v dd = 5.5v, xt mode f osc = 10 mhz, v dd = 3.0v, hs mode f osc = 20 mhz, v dd = 5.5v, hs mode f osc = 32 khz, v dd = 3.0v, lp mode, commercial f osc = 32 khz, v dd = 3.0v, lp mode, industrial power-down current (5) i pd ? ? ? ? 0.25 0.25 1.8 2.0 4.0 5.0 7.0 8.0 a a a a v dd = 3.0v, wdt disabled, commercial v dd = 3.0v, wdt disabled, industrial v dd = 5.5v, wdt disabled, commercial v dd = 5.5v, wdt disabled, industrial watchdog timer current ? i wdt ? ? ? ? 3.75 3.75 8 10 8.0 9.0 20 22 a a a a v dd = 3.0v, commercial v dd = 3.0v, industrial v dd = 5.5v*, commercial v dd = 5.5v*, industrial * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? . 5: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss .
pic16c5x ds30453c-page 118 preliminary ? 2000 microchip technology inc. 15.2 dc characteristics: pic16c54c/c55a/c56a/c57c/c58b-04e, 20e (extended) pic16cr54c/cr56a/cr57c/cr58b -04e, 20e (extended) dc characteristics power supply pins standard operating conditions (unless otherwise specified) operating temperature ? 40 c t a +125 c (extended) characteristic sym min typ (1) max units conditions supply voltage xt, rc, lp and hs options hs option v dd 3.0 4.5 ? ? 5.5 5.5 v v hs option from 0 - 10mhz hs option from 0 - 20mhz ram data retention voltage (2) v dr ? 1.5* ? v device in sleep mode v dd start voltage to ensure power-on reset v por ? v ss ? v see section 7.4 for details on power-on reset v dd rise rate to ensure power-on reset s vdd 0.05* ?? v/ms see section 7.4 for details on power-on reset supply current (3) xt and rc (4) options hs option i dd ? ? 1.8 9.0 3.3 20 ma ma f osc = 4.0 mhz, v dd = 5.5v f osc = 20 mhz, v dd = 5.5v power-down current (5) i pd ? ? ? 0.3 10 12 17 50 60 a a a v dd = 3.0v, wdt disabled v dd = 4.5v, wdt disabled v dd = 5.5v, wdt disabled watchdog timer current ? i wdt ? ? 4.5 8 14 14 18 30 a a a v dd = 3.0v v dd = 4.5v* v dd = 5.5v* * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? . 5: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss .
? 2000 microchip technology inc. preliminary ds30453c-page 119 pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/c58b/cr58b 15.3 dc characteristics: pic16lc5x-04, pic16lcr5x-04 (commercial) pic16lc5x-04i, pic16lcr5x-04i (industrial) dc characteristics power supply pins standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) characteristic sym min typ (1) max units conditions supply voltage xt and rc options lp options v dd 3.0 2.5 ? ? 5.5 5.5 v v ram data retention voltage (2) v dr ? 1.5* ? v device in sleep mode v dd start voltage to ensure power-on reset v por ? v ss ? v see section 7.4 for details on power-on reset v dd rise rate to ensure power-on reset s vdd 0.05* ?? v/ms see section 7.4 for details on power-on reset supply current (3)(4) i dd ? ? ? ? 0.4 0.5 11 14 0.6 2.4 27 35 ma ma a a f osc = 4.0 mhz, v dd = 2.5v, xt mode f osc = 4.0 mhz, v dd = 5.5v, xt mode f osc = 32 khz, v dd = 2.5v, lp mode, commercial f osc = 32 khz, v dd = 2.5v, lp mode, industrial power-down current (5) i pd ? ? 0.25 0.25 2 3 a a v dd = 2.5v, wdt disabled, commercial v dd = 2.5v, wdt disabled, industrial watchdog timer current ? i wdt ? ? 0.8 1 3 5 a a v dd = 2.5v, commercial v dd = 2.5v, industrial * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through r ext . the current through the resistor can be estimated by the formula: i r = v dd /2r ext (ma) with r ext in k ? . 5: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss .
pic16c5x ds30453c-page 120 preliminary ? 2000 microchip technology inc. 15.4 dc characteristics: pic16c54b/c54c/c55a/c56a/c57c/c58b-04, 20 (commercial, industrial, extended) pic16lc54b/lc54c/lc55a/lc56a/lc57c/lc58b-04 (commercial, industrial) pic16 c r54c/cr56a/cr57c/cr58b-04, 20 (commercial, industrial, extended) pic16lcr54b/lcr54c/lcr56a/lcr57c/lcr58b-04 (commercial, industrial) dc characteristics all pins except power supply pins standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 15.1, section 15.2 and section 15.3. characteristic sym min typ (1) max units conditions input low voltage i/o ports i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) osc1 v il v ss v ss v ss v ss v ss ? ? ? ? ? 0.8 v 0.15 v dd 0.15 v dd 0.15 v dd 0.15 v dd 0.3 v dd v v v v v ? 4.5v ? 2000 microchip technology inc. preliminary ds30453c-page 121 pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/c58b/cr58b 15.5 timing parameter symbology and load conditions the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 2. tpps t f frequency t time lowercase subscripts (pp) and their meanings: pp 2to mcmclr ck clkout osc oscillator cy cycle time os osc1 drt device reset timer t0 t0cki io i/o port wdt watchdog timer uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance figure 15-3: load conditions - pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/c58b/cr58b, pic16cr5x c l v ss pin c l = 50 pf for all pins except osc2 15 pf for osc2 in xt, hs or lp options when external clock is used to drive osc1
pic16c5x ds30453c-page 122 preliminary ? 2000 microchip technology inc. 15.6 timing diagrams and specifications figure 15-4: external clock timing - pic16c5x, pic16cr5x table 15-1: external clock timing requirements - pic16c5x, pic16cr5x ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 15.1, section 15.2 and section 15.3. parameter no. sym characteristic min typ (1) max units conditions f osc external clkin frequency (2) dc ? 4.0 mhz xt osc mode dc ? 4.0 mhz hs osc mode (04) dc ? 20 mhz hs osc mode (20) dc ? 200 khz lp osc mode oscillator frequency (2) dc ? 4.0 mhz rc osc mode dc ? 4.0 mhz xt osc mode dc ? 4.0 mhz hs osc mode (04) dc ? 20 mhz hs osc mode (20) dc ? 200 khz lp osc mode 1t osc external clkin period (2) 250 ?? ns xt osc mode 250 ?? ns hs osc mode (04) 50 ?? ns hs osc mode (20) 5.0 ?? s lp osc mode oscillator period (2) 250 ?? ns rc osc mode 250 ? 2,200 ns xt osc mode 250 ? 250 ns hs osc mode (04) 50 ? 250 ns hs osc mode (20) 5.0 ? 200 s lp osc mode * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guid- ance only and are not tested. 2: all specified values are based on characterization data for that particular oscillator type under standard oper- ating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ? max ? cycle time limit is ? dc ? (no clock) for all devices. 3: instruction cycle period (t cy ) equals four times the input oscillator time base period. osc1 clkout q4 q1 q2 q3 q4 q1 133 44 2
? 2000 microchip technology inc. preliminary ds30453c-page 123 pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/c58b/cr58b 2t cy instruction cycle time (3) ? 4/f osc ?? 3 tosl, tosh clock in (osc1) low or high time 50* ?? ns xt oscillator 20* ?? ns hs oscillator 2.0* ?? s lp oscillator 4 tosr, tosf clock in (osc1) rise or fall time ?? 25* ns xt oscillator ?? 25* ns hs oscillator ?? 50* ns lp oscillator table 15-1: external clock timing requirements - pic16c5x, pic16cr5x (con ? t) ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 15.1, section 15.2 and section 15.3. parameter no. sym characteristic min typ (1) max units conditions * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guid- ance only and are not tested. 2: all specified values are based on characterization data for that particular oscillator type under standard oper- ating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ? max ? cycle time limit is ? dc ? (no clock) for all devices. 3: instruction cycle period (t cy ) equals four times the input oscillator time base period.
pic16c5x ds30453c-page 124 preliminary ? 2000 microchip technology inc. figure 15-5: clkout and i/o timing - pic16c5x, pic16cr5x table 15-2: clkout and i/o timing requirements - pic16c5x, pic16cr5x ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 15.1, section 15.2 and section 15.3. parameter no. sym characteristic min typ (1) max units 10 tosh2ckl osc1 to clkout (2) ? 15 30** ns 11 tosh2ckh osc1 to clkout (2) ? 15 30** ns 12 tckr clkout rise time (2) ? 5.0 15** ns 13 tckf clkout fall time (2) ? 5.0 15** ns 14 tckl2iov clkout to port out valid (2) ?? 40** ns 15 tiov2ckh port in valid before clkout (2) 0.25 tcy+30* ?? ns 16 tckh2ioi port in hold after clkout (2) 0* ?? ns 17 tosh2iov osc1 (q1 cycle) to port out valid (3) ?? 100* ns 18 tosh2ioi osc1 (q2 cycle) to port input invalid (i/o in hold time) tbd ?? ns 19 tiov2osh port input valid to osc1 (i/o in setup time) tbd ?? ns 20 tior port output rise time (3) ? 10 25** ns 21 tiof port output fall time (3) ? 10 25** ns * these parameters are characterized but not tested. ** these parameters are design targets and are not tested. no characterization data available at this time. note 1: data in the typical ( ? typ ? ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: measurements are taken in rc mode where clkout output is 4 x t osc . 3: see figure 15-3 for loading conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 18 15 11 12 16 old value new value note: refer to figure 19-1 for load conditions. 19
? 2000 microchip technology inc. preliminary ds30453c-page 125 pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/c58b/cr58b figure 15-6: reset, watchdog timer, and device reset timer timing - pic16c5x, pic16cr5x table 15-3: reset, watchdog timer, and device reset timer - pic16c5x, pic16cr5x ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 15.1, section 15.2 and section 15.3. parameter no. sym characteristic min typ (1) max units conditions 30 tmcl mclr pulse width (low) 1000* ?? ns v dd = 5.0v 31 twdt watchdog timer time-out period (no prescaler) 9.0* 18* 30* ms v dd = 5.0v (commercial) 32 t drt device reset timer period 9.0* 18* 30* ms v dd = 5.0v (commercial) 34 tio z i/o hi-impedance from mclr low 100* 300* 1000* ns * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guid- ance only and are not tested. v dd mclr internal por drt time-out internal reset watchdog timer reset 32 31 34 i/o pin 32 32 34 (note 1) note 1: i/o pins must be taken out of hi-impedance mode by enabling the output drivers in software. 30
pic16c5x ds30453c-page 126 preliminary ? 2000 microchip technology inc. figure 15-7: timer0 clock timings - pic16c5x, pic16cr5x table 15-4: timer0 clock requirements - pic16c5x, pic16cr5x ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) ? 40 c t a +85 c (industrial) ? 40 c t a +125 c (extended) operating voltage v dd range is described in section 15.1, section 15.2 and section 15.3. param no. sym characteristic min typ (1) max units conditions 40 tt0h t0cki high pulse width- no prescaler 0.5 t cy + 20* ?? ns - with prescaler 10* ?? ns 41 tt0l t0cki low pulse width - no prescaler 0.5 t cy + 20* ?? ns - with prescaler 10* ?? ns 42 tt0p t0cki period 20 or t cy + 40 * n ?? ns whichever is greater. n = prescale value (1, 2, 4,..., 256) * these parameters are characterized but not tested. note 1: data in the typical ( ? typ ? ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. t0cki 40 41 42
? 2000 microchip technology inc. preliminary ds30453c-page 127 pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/c58b/cr58b 16.0 dc and ac characteristics - pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/c58b/cr58b the graphs and tables provided in this section are for design guidance and are not tested. in some graphs or tables, the data presented is outside specified operating range (e.g., outside specified v dd range). this is for information only and devices will operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. ? typical ? represents the mean of the distribution, while ? max ? or ? min ? represents (mean + 3 ) and (mean ? 3 ) respectively, where is standard deviation. figure 16-1: typical rc oscillator frequency vs. temperature table 16-1: rc oscillator frequencies c ext r ext average fosc @ 5 v, 25 c 20 pf 3.3 k 4.973 mhz 27% 5 k 3.82 mhz 21% 10 k 2.22 mhz 21% 100 k 262.15 khz 31% 100 pf 3.3 k 1.63 mhz 13% 5 k 1.19 mhz 13% 10 k 684.64 khz 18% 100 k 71.56 khz 25% 300 pf 3.3 k 660 khz 10% 5.0 k 484.1 khz 14% 10 k 267.63 khz 15% 160 k 29.44 khz 19% the frequencies are measured on dip packages. the percentage variation indicated here is part-to-part variation due to normal process distribution. the variation indicated is 3 standard deviation from average value for v dd = 5 v. f osc f osc (25 c) 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 010 20253040506070 t( c) frequency normalized to +25 c v dd = 5.5 v v dd = 3.5 v r ext 10 k ? c ext = 100 pf 0.88
pic16c5x ds30453c-page 128 preliminary ? 2000 microchip technology inc. figure 16-2: typical rc oscillator frequency vs. v dd , c ext = 20 p f figure 16-3: typical rc oscillator frequency vs. v dd , c ext = 100 p f v dd (volts) f osc (mhz) c ext =20pf, t=25c r=100k r=10k r=3.3k 2.5 3 3.5 4.5 5.5 4 56 r=5.0k 6.00 5.00 4.00 2.00 0 3.00 1.00 2.5 3 3.5 4.5 5.5 4 56 v dd (volts) 1.80 1.60 1.40 0.60 0 1.00 0.20 c ext =20pf, t=25c r=100k r=10k r=5.0k r=3.3k f osc (mhz)
? 2000 microchip technology inc. preliminary ds30453c-page 129 pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/c58b/cr58b figure 16-4: typical rc oscillator frequency vs. v dd , c ext = 300 p f figure 16-5: typical i pd vs. v dd , watchdog disabled (25 c) v dd (volts) f osc (mhz) 2.5 3 3.5 4.5 5.5 4 56 c ext =20pf, t=25c r=100k r=10k r=5.0k r=3.3k 600.0 500.0 400.0 200.0 0 300.0 100.0 700.0 v dd (volts) i pd (ua) 25 20 15 5 0 2.5 3 3.5 4.5 5.5 4 56 10
pic16c5x ds30453c-page 130 preliminary ? 2000 microchip technology inc. figure 16-6: typical i pd vs. v dd , watchdog enabled (25 c) figure 16-7: typical i pd vs. v dd , watchdog enabled ( ? 40 c, 85 c) v dd (volts) i pd (ua) 25 20 15 0 2.5 3 4.5 5.5 4 56 10 5 3.5 v dd (volts) i pd (ua) 35 15 5 0 2.5 3 3.5 4.5 5.5 4 56 10 ( - 4 0 c ) ( + 8 5 c ) 20 25 30
? 2000 microchip technology inc. preliminary ds30453c-page 131 pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/c58b/cr58b figure 16-8: v th (input threshold trip point voltage) of i/o pins vs. v dd figure 16-9: v ih , v il of mclr , t0cki and osc1 (in rc mode) vs. v dd 2.00 1.80 1.60 1.40 1.20 1.00 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 0.80 0.60 5.5 6.0 t y p ( + 2 5 c ) v th (volts) 3.5 3.0 2.5 2.0 1.5 1.0 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 0.5 0.0 5.5 6.0 v ih , v il (volts) 4.0 4.5 v i h m i n ( ? 4 0 c t o + 8 5 c ) v i h m a x ( ? 4 0 c t o + 8 5 c ) v i h t y p + 2 5 c v i l m i n ( ? 4 0 c t o + 8 5 c ) v i l m a x ( ? 4 0 c t o + 8 5 c ) v i l t y p + 2 5 c note: these input pins have schmitt trigger input buffers.
pic16c5x ds30453c-page 132 preliminary ? 2000 microchip technology inc. figure 16-10: v th (input threshold trip point voltage) of osc1 input (in xt, hs and lp modes) vs. v dd figure 16-11: typical i dd vs. frequency (wdt dis, rc mode @ 20 p f, 2 5 c) 2.4 2.2 2.0 1.8 1.6 1.4 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 1.2 1.0 5.5 6.0 t y p ( + 2 5 c ) v th (volts) 2.6 2.8 3.0 3.2 3.4 10 100 1000 10000 0.1 1 10 freq(mhz) i dd ( a) 5.5v 4.5v 3.5v 2.5v
? 2000 microchip technology inc. preliminary ds30453c-page 133 pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/c58b/cr58b figure 16-12: typical i dd vs. frequency (wdt dis, rc mode @ 100 p f, 2 5 c) figure 16-13: typical i dd vs. frequency (wdt dis, rc mode @ 300 p f, 2 5 c) 10 100 1000 10000 0.01 0.1 1 10 freq(mhz) i dd (ua) 5.5v 4.5v 3.5v 2.5v 10 1000 10000 0.01 0.1 1 freq(mhz) i dd ( a) 100 5.5v 4.5v 3.5v 2.5v
pic16c5x ds30453c-page 134 preliminary ? 2000 microchip technology inc. figure 16-14: wdt timer time-out period vs. v dd table 16-2: input capacitance 50 45 40 35 30 25 20 15 10 5 234567 v dd (volts) wdt period (ms) typ +125 c typ +85 c typ +25 c typ ? 40 c pin typical capacitance (pf) 18l pdip 18l soic ra port 5.0 4.3 rb port 5.0 4.3 mclr 17.0 17.0 osc1 4.0 3.5 osc2/clkout 4.3 3.5 t0cki 3.2 2.8 all capacitance values are typical at 25 c. a part-to-part variation of 25% (three standard deviations) should be taken into account.
? 2000 microchip technology inc. preliminary ds30453c-page 135 pic16c54c/cr54c/c55a/c56a/cr56a/c57c/cr57c/c58b/cr58b figure 16-15: i oh vs. v oh , v dd = 3 v figure 16-16: i oh vs. v oh , v dd = 5 v 0 ? 5 ? 10 ? 15 ? 20 ? 25 0 0.5 1.0 1.5 2.0 2.5 v oh (volts) i oh (ma) min +85 c 3.0 typ +25 c max ? 40 c 0 ? 10 ? 20 ? 30 ? 40 1.5 2.0 2.5 3.0 3.5 4.0 v oh (volts) i oh (ma) typ ? 40 c 4.5 5.0 typ +85 c typ +125 c typ +25 c figure 16-17: i ol vs. v ol , v dd = 3 v figure 16-18: i ol vs. v ol , v dd = 5 v 45 40 35 30 25 20 15 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 v ol (volts) i ol (ma) min +85 c max ? 40 c typ +25 c 3.0 90 80 70 60 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 v ol (volts) i ol (ma) min +85 c max ? 40 c typ +25 c 3.0
pic16c5x ds30453c-page 136 preliminary ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. preliminary ds30453c-page 137 pic16c5x 17.0 packaging information 18-lead plastic dual in-line (p) ? 300 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 9.40 7.87 .430 .370 .310 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.78 1.46 1.14 .070 .058 .045 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 22.99 22.80 22.61 .905 .898 .890 d overall length 6.60 6.35 6.10 .260 .250 .240 e1 molded package width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.68 3.30 2.92 .145 .130 .115 a2 molded package thickness 4.32 3.94 3.56 .170 .155 .140 a top to seating plane 2.54 .100 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 2 d n e1 c eb e p a2 l b1 b a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-007 significant characteristic
pic16c5x ds30453c-page 138 preliminary ? 2000 microchip technology inc. 28-lead skinny plastic dual in-line (sp) ? 300 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 8.89 8.13 .430 .350 .320 eb overall row spacing 0.56 0.48 0.41 .022 .019 .016 b lower lead width 1.65 1.33 1.02 .065 .053 .040 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 35.18 34.67 34.16 1.385 1.365 1.345 d overall length 7.49 7.24 6.99 .295 .285 .275 e1 molded package width 8.26 7.87 7.62 .325 .310 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.43 3.30 3.18 .135 .130 .125 a2 molded package thickness 4.06 3.81 3.56 .160 .150 .140 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 c eb e p l a2 b b1 a a1 notes: jedec equivalent: mo-095 drawing no. c04-070 * controlling parameter dimension d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. significant characteristic
? 2000 microchip technology inc. preliminary ds30453c-page 139 pic16c5x 28-lead plastic dual in-line (p) ? 600 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 17.27 16.51 15.75 .680 .650 .620 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.78 1.27 0.76 .070 .050 .030 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.05 .135 .130 .120 l tip to seating plane 37.21 36.32 35.43 1.465 1.430 1.395 d overall length 14.22 13.84 12.83 .560 .545 .505 e1 molded package width 15.88 15.24 15.11 .625 .600 .595 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 4.06 3.81 3.56 .160 .150 .140 a2 molded package thickness 4.83 4.45 4.06 .190 .175 .160 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 c eb e p l a2 b a1 a b1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: mo-011 drawing no. c04-079 significant characteristic
pic16c5x ds30453c-page 140 preliminary ? 2000 microchip technology inc. 18-lead plastic small outline (so) ? wide, 300 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.30 0.27 0.23 .012 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 11.73 11.53 11.33 .462 .454 .446 d overall length 7.59 7.49 7.39 .299 .295 .291 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units l c h 45 1 2 d p n b e1 e a2 a1 a * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-051 significant characteristic
? 2000 microchip technology inc. preliminary ds30453c-page 141 pic16c5x 28-lead plastic small outline (so) ? wide, 300 mil (soic) foot angle top 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.33 0.28 0.23 .013 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 18.08 17.87 17.65 .712 .704 .695 d overall length 7.59 7.49 7.32 .299 .295 .288 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c 45 h a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-052 significant characteristic
pic16c5x ds30453c-page 142 preliminary ? 2000 microchip technology inc. 20-lead plastic shrink small outline (ss) ? 209 mil, 5.30 mm (ssop) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.38 0.32 0.25 .015 .013 .010 b lead width 203.20 101.60 0.00 8 4 0 foot angle 0.25 0.18 0.10 .010 .007 .004 c lead thickness 0.94 0.75 0.56 .037 .030 .022 l foot length 7.34 7.20 7.06 .289 .284 .278 d overall length 5.38 5.25 5.11 .212 .207 .201 e1 molded package width 8.18 7.85 7.59 .322 .309 .299 e overall width 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.83 1.73 1.63 .072 .068 .064 a2 molded package thickness 1.98 1.85 1.73 .078 .073 .068 a overall height 0.65 .026 p pitch 20 20 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: mo-150 drawing no. c04-072 significant characteristic
? 2000 microchip technology inc. preliminary ds30453c-page 143 pic16c5x 28-lead plastic shrink small outline (ss) ? 209 mil, 5.30 mm (ssop) * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: ms-150 drawing no. c04-073 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.38 0.32 0.25 .015 .013 .010 b lead width 203.20 101.60 0.00 8 4 0 foot angle 0.25 0.18 0.10 .010 .007 .004 c lead thickness 0.94 0.75 0.56 .037 .030 .022 l foot length 10.34 10.20 10.06 .407 .402 .396 d overall length 5.38 5.25 5.11 .212 .207 .201 e1 molded package width 8.10 7.85 7.59 .319 .309 .299 e overall width 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.83 1.73 1.63 .072 .068 .064 a2 molded package thickness 1.98 1.85 1.73 .078 .073 .068 a overall height 0.65 .026 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters* inches units 2 1 d p n b e1 e l c a2 a1 a significant characteristic
pic16c5x ds30453c-page 144 preliminary ? 2000 microchip technology inc. 18-lead ceramic dual in-line with window (jw) ? 300 mil (cerdip) 3.30 3.56 3.81 5.33 5.08 4.83 .210 .200 .190 w2 window length .150 .140 .130 w1 window width 10.80 9.78 8.76 .425 .385 .345 eb overall row spacing 0.53 0.47 0.41 .021 .019 .016 b lower lead width 1.52 1.40 1.27 .060 .055 .050 b1 upper lead width 0.30 0.25 0.20 .012 .010 .008 c lead thickness 3.81 3.49 3.18 .150 .138 .125 l tip to seating plane 23.37 22.86 22.35 .920 .900 .880 d overall length 7.49 7.37 7.24 .295 .290 .285 e1 ceramic pkg. width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.76 0.57 0.38 .030 .023 .015 a1 standoff 4.19 4.06 3.94 .165 .160 .155 a2 ceramic package height 4.95 4.64 4.32 .195 .183 .170 a top to seating plane 2.54 .100 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 2 d n w2 e1 w1 c eb e p l a2 b b1 a a1 * controlling parameter significant characteristic jedec equivalent: mo-036 drawing no. c04-010
? 2000 microchip technology inc. preliminary ds30453c-page 145 pic16c5x 28-lead ceramic dual in-line with window (jw) ? 600 mil (cerdip) 7.37 7.11 6.86 .290 .280 .270 w window diameter 18.03 16.76 15.49 .710 .660 .610 eb overall row spacing 0.58 0.51 0.41 .023 .020 .016 b lower lead width 1.65 1.46 1.27 .065 .058 .050 b1 upper lead width 0.30 0.25 0.20 .012 .010 .008 c lead thickness 3.81 3.49 3.18 .150 .138 .125 l tip to seating plane 37.85 37.08 36.32 1.490 1.460 1.430 d overall length 13.36 13.21 13.06 .526 .520 .514 e1 ceramic pkg. width 15.88 15.24 15.11 .625 .600 .595 e shoulder to shoulder width 1.52 0.95 0.38 .060 .038 .015 a1 standoff 4.19 4.06 3.94 .165 .160 .155 a2 ceramic package height 5.08 4.70 4.32 .200 .185 .170 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 w c e eb p a2 l b1 b a1 a * controlling parameter significant characteristic jedec equivalent: mo-103 drawing no. c04-013
pic16c5x ds30453c-page 146 preliminary ? 2000 microchip technology inc. 17.1 package marking information xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn 18-lead pdip 28-lead skinny pdip (.300") yywwnnn pic16c56a- 0023cba example example 04i/p456 0023cba pic16c55a- yywwnnn 28-lead pdip (.600") 04/p126 0042cda example pic16c55a- xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxx xxxxxxxxxxxxxxx xxxxxxxxxxxxxxx 18-lead soic xxxxxxxxxxxx yywwnnn 28-lead soic yywwnnn xxxxxxxxxxxxxxxxxxxx 20-lead ssop yywwnnn xxxxxxxxxxx example pic16c54c- 0018cdk 04/s0218 example 0015cbk pic16c57c- example 04/218 0020cbp pic16c54c 28-lead ssop xxxxxxxxxxxx example 0025cbk pic16c57c- 04/ss123 xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx 04/so xxxxxxxxxxx xxxxxxxxxxxx 04i/p456 xxxxxxxxxxxxxxxxxxxx yywwnnn
? 2000 microchip technology inc. preliminary ds30453c-page 147 pic16c5x xxxxxxxx xxxxxxxx yywwnnn 18-lead cerdip windowed 28-lead cerdip windowed 0001cba example example pic16c54c /jw xxxxxxxxxxx yywwnnn xxxxxxxxxxx pic16c57c /jw 0038cba legend: xx...x customer specific information* yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ? 01 ? ) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev#, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. xxxxxxxxxxx
pic16c5x ds30453c-page 148 preliminary ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. preliminary ds30453c-page 149 pic16c5x appendix a: compatibility to convert code written for pic16cxx to pic16c5x, the user should take the following steps: 1. check any call , goto or instructions that modify the pc to determine if any program memory page select operations (pa2, pa1, pa0 bits) need to be made. 2. revisit any computed jump operations (write to pc or add to pc, etc.) to make sure page bits are set properly under the new scheme. 3. eliminate any special function register page switching. redefine data variables to reallocate them. 4. verify all writes to status, option, and fsr registers since these have changed. 5. change reset vector to proper value for processor used. 6. remove any use of the addlw and sublw instructions. 7. rewrite any code segments that use interrupts.
pic16c5x ds30453c-page 150 preliminary ? 2000 microchip technology inc. notes:
? 2000 microchip technology inc. preliminary ds30453c-page 151 pic16c5x index a absolute maximum ratings ........................... 61, 81, 93, 115 alu ...................................................................................... 9 applications .......................................................................... 5 architectural overview ......................................................... 9 assembler mpasm assembler .................................................... 55 b block diagram on-chip reset circuit ................................................ 36 pic16c5x series ....................................................... 10 timer0 ........................................................................ 27 tmr0/wdt prescaler ................................................ 30 watchdog timer ......................................................... 40 brown-out protection circuit .............................................. 41 c carry bit ............................................................................... 9 clocking scheme ............................................................... 13 cmos technology ............................................................... 1 code protection ........................................................... 31, 42 configuration bits ............................................................... 31 configuration word ............................................................ 31 pic16c54/c54a/c55/c56/c57 .................................. 32 pic16cr54a/c54c/cr54c/c55a/c56a/ cr56a/c57c/cr57c/c58b/cr58b .......................... 31 d dc and ac characteristics - pic16c54/55/56/57 ............. 73 dc and ac characteristics - pic16c54a ........................ 105 dc and ac characteristics - pic16c54c/cr54c/ c55a/c56a/cr56a/c57c/cr57c/c58b/cr58b ............ 127 dc characteristics ............................................... 82, 94, 117 pic16c54/55/56/57 ........................... 62, 63, 64, 65, 66 pic16c54a ................................................................ 94 pic16cr54a ............................................................. 82 development support ........................................................ 55 device varieties ................................................................... 7 digit carry bit ....................................................................... 9 e electrical characteristics pic16c54/55/56/57 ................................................... 61 pic16c54a ................................................................ 93 pic16c54c/cr54c/c55a/c56a/cr56a/ c57c/cr57c/c58b/cr58b .................................... 115 pic16cr54a ............................................................. 81 errata ................................................................................... 4 external power-on reset circuit ........................................ 37 f family of devices pic16c5x .................................................................... 6 fsr ................................................................................... 36 fsr register ..................................................................... 22 h high-performance risc cpu ............................................. 1 i i/o interfacing .................................................................... 25 i/o ports ............................................................................ 25 i/o programming considerations ...................................... 26 id locations ................................................................. 31, 42 indf .................................................................................. 36 indf register .................................................................... 22 indirect data addressing ................................................... 22 instruction cycle ................................................................ 13 instruction flow/pipelining ................................................. 13 instruction set summary ................................................... 43 k keeloq ? evaluation and programming tools .................. 58 l loading of pc .............................................................. 21, 22 m mclr ................................................................................ 36 memory map ...................................................................... 15 pic16c54/cr54/c55 ................................................ 15 pic16c56/cr56 ........................................................ 15 pic16c57/cr57/c58/cr58 ...................................... 15 memory organization ........................................................ 15 data memory ............................................................. 16 program memory ....................................................... 15 mplab integrated development environment software ... 55 o one-time-programmable (otp) devices ........................... 7 option ............................................................................. 36 option register ............................................................... 20 osc selection .................................................................... 31 oscillator configurations .................................................... 33 oscillator types hs .............................................................................. 33 lp .............................................................................. 33 rc ............................................................................. 33 xt .............................................................................. 33
pic16c5x ds30453c-page 152 preliminary ? 2000 microchip technology inc. p package marking information .......................................... 146 packaging information ..................................................... 137 pc ...................................................................................... 21 pcl .................................................................................... 36 peripheral features .............................................................. 1 pic16c54/55/56/57 product identification system .......... 156 pic16c5x product identification system ......................... 155 picdem-1 low-cost picmicro demo board ..................... 57 picdem-2 low-cost pic16cxx demo board .................. 57 picdem-3 low-cost pic16cxxx demo board ................ 57 picstart ? plus entry level development system ........ 57 pin configurations ................................................................ 2 pinout description - pic16c54s, pic16cr54, pic16c56, pic16cr56, pic16c58, pic16cr58 ..................................................... 11 pinout description - pic16c55, pic16c57, pic16cr57 ........................................................................ 12 por device reset timer (drt) ................................... 31, 39 pd ........................................................................ 35, 41 power-on reset (por) .................................. 31, 36, 37 to ........................................................................ 35, 41 porta ......................................................................... 25, 36 portb ......................................................................... 25, 36 portc ......................................................................... 25, 36 power-down mode (sleep) .............................................. 42 prescaler ............................................................................ 30 pro mate ? ii universal programmer .............................. 57 program counter ................................................................ 21 q q cycles ............................................................................. 13 quick-turnaround-production (qtp) devices ..................... 7 r rc oscillator ...................................................................... 34 read only memory (rom) devices ..................................... 7 read-modify-write ............................................................. 26 register file map pic16c54, pic16cr54, pic16c55, pic16c56, pic16cr56 ............................................. 16 pic16c57/cr57 ........................................................ 17 pic16c58/cr58 ........................................................ 17 registers special function ........................................................ 18 reset ............................................................................... 35 reset .................................................................................. 31 reset on brown-out ......................................................... 41 s serialized quick-turnaround-production (sqtp) devices ................................................................................ 7 sleep ......................................................................... 31, 42 software simulator (mplab-sim) ..................................... 56 special features of the cpu ............................................. 31 special function registers ................................................ 18 stack .................................................................................. 22 status ............................................................................. 36 status register .......................................................... 9, 19 t timer0 switching prescaler assignment ............................... 30 timer0 (tmr0) module .............................................. 27 tmr0 with external clock ......................................... 29 timing diagrams and specifications ............. 68, 88, 99, 122 timing parameter symbology and load conditions ............................................. 67, 87, 98, 121 tmr0 ................................................................................. 36 tris ................................................................................... 36 tris registers .................................................................. 25 u uv erasable devices ........................................................... 7 w w register ......................................................................... 36 wake-up from sleep ........................................................ 42 watchdog timer (wdt) ............................................... 31, 39 period ........................................................................ 39 programming considerations .................................... 39 www, on-line support ...................................................... 4 z zero bit ................................................................................. 9
? 2000 microchip technology inc. preliminary ds30453c-page 153 pic16c5x systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip ? s development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-786-7302 for the rest of the world. trademarks: the microchip name, logo, pic, picmicro, picstart, picmaster, pro mate and mplab are registered trademarks of microchip technology incorpo- rated in the u.s.a. and other countries. flex rom and fuzzy lab are trademarks and sqtp is a service mark of microchip in the u.s.a. all other trademarks mentioned herein are the property of their respective companies. on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user ? s guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development sys- tems, technical information and more listing of seminars and events 991103
pic16c5x ds30453c-page 154 preliminary ? 1998 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds30453c pic16c5x
? 2000 microchip technology inc. preliminary ds30453c-page 155 pic16c5x pic16c5x product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. part no. x /xx xxx pattern package temperature range device device pic16c5x (2) , pic16c5xt (3) pic16lc5x (2) , pic16lc5xt (3) pic16cr5x (2) , pic16cr5xt (3) pic16lcr5x (2) , pic16lcr5xt (3) pic16lv5x (2) , pic16lv5xt (3) temperature range b (1) i e =0 c to +70 c (commercial) =-40 c to +85 c (industrial) =-40 c to +125 c (automotive) package jw p so sp ss = windowed cerdip = pdip = soic (gull wing, 300 mil body) = skinny pdip (28-pin, 300 mil body) = ssop (209 mil body) pattern 3-digit pattern code for qtp, rom (blank otherwise) examples: a) pic16c54a -04/p 301 = commercial temp., pdip package, 4mhz, normal v dd limitis, qtp pattern #301. b) pic16lc58a - 04i/so = industrial temp., soic package, 4mhz, extended v dd limits. c) pic16cr54a - 10i/p355 = rom program memory, industrial temp., pdip package, 10mhz, normal v dd limits. note 1: b = blank 2: c = standard v dd range lc = extended v dd range cr = rom version, standard v dd range lcr = rom version, extended v dd range lv = low voltage v dd range 3: t = in tape and reel - soic, ssop packages only. 4: uv erasable devices are tested to all available voltage/frequency options. erased devices are oscillator type 04. the user can select 04, 10 or 20 oscil- lators by programmng the appropriate configuration bits.
ds30453c-page 156 preliminary ? 2000 microchip technology inc. pic16c5x pic16c54/55/56/57 product identification system to order or obtain information (e.g., on pricing or delivery) refer to the factory or the listed sales office. sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 786-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. part no. -xx x /xx xxx pattern package temperature range oscillator type device device pic16c54, pic16c54t (2) pic16c55, pic16c55t (2) pic16c56, pic16c56t (2) pic16c57, pic16c57t (2) oscillator type rc lp xt hs 10 b (1) = resistor capacitor = low power crystal = standard crystal/resonator = high speed crystal = 10 mhz crystal = no type for jw (3) devices temperature range b (1) i e =0 c to +70 c (commercial) =-40 c to +85 c (industrial) =-40 c to +125 c (automotive) package jw p s so sp ss = windowed cerdip = pdip = die in waffle pack = soic (gull wing, 300 mil body) = skinny pdip (28 pin, 300 mil body) = ssop (209 mil body) pattern 3-digit pattern code for qtp (blank otherwise) examples: a) pic16c54 - xt/pxxx = "xt" oscillator, commercial temp., pdip, qtp pattern. b) pic16c55 - xti/so = "xt" oscillator, industrial temp., soic (otp device) c) pic16c55 /jw = commercial temp. cerdip with window. d) pic16c57 - rc/s = "rc" oscillator, com- mercial temp., dice in waffle pack. note 1: b = blank 2: t = in tape and reel - soic, ssop packages only. 3: uv erasable devices are tested to all available voltage/frequency options. erased devices are oscillator type rc. the user can select rc, lp, xt or hs oscillators by programming the appro- priate configuration bits.
? 2000 microchip technology inc. preliminary ds30453c-page 157 pic16c5x notes:
information contained in this publication regarding device applications and the like is intended through suggestion only and ma y be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is give n and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip ? s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under an y intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. a ll rights reserved. all other trademarks mentioned herein are the property of their respective companies. ds30453c-page 158 preliminary ? 2000 microchip technology inc. all rights reserved. ? 2000 microchip technology incorporated. printed in the usa. 7/00 printed on recycled paper. americas corporate office microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-786-7200 fax: 480-786-7277 technical support: 480-786-7627 web address: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 2 lan drive, suite 120 westford, ma 01886 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit microchip technology inc. tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york microchip technology inc. 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 americas (continued) toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific china - beijing microchip technology, beijing unit 915, 6 chaoyangmen bei dajie dong erhuan road, dongcheng district new china hong kong manhattan building beijing, 100027, p.r.c. tel: 86-10-85282100 fax: 86-10-85282104 china - shanghai microchip technology unit b701, far east international plaza, no. 317, xianxia road shanghai, 200051, p.r.c. tel: 86-21-6275-5700 fax: 86-21-6275-5060 hong kong microchip asia pacific unit 2101, tower 2 metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 india microchip technology inc. india liaison office no. 6, legacy, convent road bangalore, 560 025, india tel: 91-80-229-0061 fax: 91-80-229-0062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 asia/pacific (continued) singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore, 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan microchip technology taiwan 10f-1c 207 tung hua north road taipei, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe denmark microchip technology denmark aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france arizona microchip technology sarl parc d ? activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 m nchen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5858 fax: 44-118 921-5835 05/16/00 w orldwide s ales and s ervice microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.

▲Up To Search▲

Price & Availability of PIC16C54-XTIS

	To Download PIC16C54-XTIS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .